electrostatic discharge

This document provides estimates of future ESD device thresholds and their potential impact on ESD control practices. The threshold estimates reflect the prevailing trends in semiconductor technology as viewed by selected industry leaders. These projections are intended to provide a view of future device protection limitations driven by performance requirements and technology scaling. It also provides a common view of expected performance for device suppliers and users. Finally, these trends point to the need for continued improvements in ESD control procedures and compliance.

In Part 2 of this series we indicated that a key element in a successful static control program was the identification of those items (components, assemblies and finished products) that are sensitive to ESD and the level of their sensitivity. Damage to an ESDS device by the ESD event is determined by the device’s ability to dissipate the energy of the discharge or withstand the current levels involved. This is known as device “ESD sensitivity” or “ESD susceptibility.”

The electronics industry is continually shifting. Device density and technology is more complex. Electronics manufacturing is more heavily reliant on out‑sourcing. The ESD industry seems to have jumped into this swirling eddy headfirst. ESD control programs have mushroomed. Black has been replaced by green, blue and gold. Shielding bags dominate the warehouse. Ionizers exist along side wrist straps and ground cords. An early history of “smoke and mirrors,” magic and lofty claims of performance is rapidly and safely being relegated to the past.

Your static control program is up and running. How do you determine whether it is effective? How do you make sure your employees follow it? In Part 3, we suggested that there were at least nine critical elements to successfully developing and implementing an effective ESD control program. In Part 4, we will focus on two more of these elements: training and auditing.

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!

The electronics industry is terribly confused by the term Class 0. Particularly when it comes to electrostatic discharge (ESD) device sensitivity and how the term applies to factory controls designed to mitigate ESD. The confusion manifests itself through the many companies and engineers seeking direction on how to “become qualified to handle Class 0 devices.” They are seeking this information because their equally confused customers have imposed requirements on them to meet this mythical level of performance. Not only is Class 0 as a factory level of performance a contrived ideal, it is not a realistic or useful goal. Our purpose here is to explain reality and what is necessary for understanding device ESD sensitivity and establishing control.