Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.
Anyone who has worked in Quality or Reliability in a large corporation knows that developing and presenting credible failure cost information can be difficult. This is particularly true for ESD, where the events are invisible and not nearly as well understood as other more obvious classes of failure, such as mechanical or contamination. The “real” cost of ESD can be a hot topic of discussion each year when program budgets are being developed for manufacturing and R&D programs. The challenge is that every year there are new high-level people in the financial and planning organizations who are not technical experts and who are asking hard questions about the justification for the ESD investment. In years when revenue is down, the questions become more difficult and better evidence is often demanded. The author was directly involved in this process for 15 years, starting in 1986. At the time the following quote was a part of many ESD funding discussions; “… in the electronics industry, losses associated with ESD are estimated at between a half billion and five billion dollars annually.” The exact original reference for this assertion has been lost, at least to this author. Nonetheless it was used many times over the next few years in presentations to the corporate check writers. Furthermore, during research for background information for this article, the exact same quote appeared (unattributed) in an article from 1992  and in a book published in 2006 . Needless to say, a well-stated assertion of value can go a long way – at least in trade literature. However, this author can also report that the usefulness of this, inside the corporation, eroded much faster. By 1990, a well-known director in Bell Labs said; “… that was then… I think this problem has been solved!” Many of us would scoff at such a declaration, knowing full well that ESD problems were continuing to occur. However, the directors’ challenge was an appropriate one. His experience came from the semiconductor process world where he had seen significant ESD sources eliminated and device thresholds (albeit HBM only) steadily increase. Corporations would like their investments to be justified by more timely and relevant data and observations. They ask, “What is the “real” cost?”
With the destabilization of the economy, many companies are looking for ways to increase profits and performance within their particular industry. The electronics industry is no exception. Many electronics companies are working towards improved quality and reliability at the same rate as improving the performance of the products they manufacture.
This article focuses on methodology, techniques and tools to identify, classify and quantify ESD occurrences in back-end semiconductor and electronics assembly manufacturing. Proper methodology of detecting and measuring ESD Events in working tools handling ESD-sensitive components, identifying CDM-type of discharges and associating discharges with the specific steps of the process is described in details on a level usable to a wide range of specialists. Use of tools, such as high-speed storage oscilloscopes, special antennae, ESD detectors and monitors will be explained in detail. This article should benefit increasing numbers of process engineers who are struggling to maintain yield while the devices are getting increasingly more and more ESD-sensitive.
The ESD Association and JEDEC Collaborate on Standards Development for Harmonized Electrostatic Discharge Test Methods
In September 2006, a small group of ESD control and design stakeholders assembled in a small conference room at the LaPaloma Resort in Tucson, AZ to discuss how the ESD Association (ESDA) and the JEDEC Solid State Technology Association (JEDEC) might harmonize some of their key device (component level) standards documents. Some of the stakeholders involved in those initial discussions (and similar meetings over the next six months) were integrated circuit manufacturers, integrated circuit test manufacturers, original equipment manufacturers, integrated circuit test service providers, and representatives from the ESDA and JEDEC. This first meeting was somewhat extraordinary as these industry stakeholders were able to bring JEDEC and the ESDA to the same table to start working on the harmonization efforts after other previous attempts failed. The key individual sponsoring this meeting was Kay Adams, the ESDA President in 2006-2007.