Digital “Noise” Common-mode Coupling Mechanisms in the Z-Axis

The development of “digital common-mode noise” within circuit devices and subsequently within circuit boards is initially formed by peak over-shoot and under-shoot currents in the power and return planes. The peak currents are attributable to the “cross-conduction” transitions in circuit devices, where the driver literally segments turning “on” before the pull-down drivers turn “off”.

The result is that at each and every rise and fall time, a partial “short circuit” is found between the output rails across the driver sets. When compared to the total signal output current driven by a circuit device, the peak power current may be 5 to 10 times higher in amplitude. These effects are displayed by Figure 1.


Figure 1: Comparative overlay of accumulated signal currents (Is) to peak power common-mode currents (Ipp). Currents (Ipp) may be exhibited as several amperes compared to amplitudes of accumulated milliamperes for signal currents (Is).

Common-mode Regions: Devices and Circuit Boards

As a result of the accumulated common-mode currents, common-mode fields are produced in essentially two regions: a) the pattern of inductance presented by signal-escapes into the ground and power planes that circumscribe circuit devices, and b) the packaging of each circuit device, as suggested by Figure 2.


Figure 2: Illustration of primary common-mode field potential regions: ECM1 around patterned layout inductance, and ECM2 within losses in circuit device packaging


The process of developing distributed inductance in the circuit board circumscription of circuit devices is called patterned layout inductance. The inductance is derived from the array of clearance “holes” (sometimes termed anti-pads) required in the planes for the passage of signals in vias. Generally, the denser the hole pattern in the planes, the more inductance is equivalently formed.

Z-Axis Coupling Within Circuit Boards

The effect of common-mode coupling into signal partitions through the stack-up of circuit boards as a result of the cross-conduction peak power currents is dependent upon the sequence of the stack-up itself. As suggested by Figures 3 and 4, when power (voltage) and image (return) planes are placed far apart and separated by signal layers, a process of flux induction may occur in the drilled signal vias as signal paths themselves. The coupling process is such that impact causing power flux induction in signals is caused, taking on a dynamic form of series modulation. The effect is noted because when a power plane is separated from its image plane. The common-mode current eddy across the apertures (holes) in the planes will set up a flux-pattern similar to that of an array of small loop antenna structures. While the phase relationship of the “holes as loop antennas” between the power and image planes would attempt to mutually cancel inductance, the distance separation causes this to be less efficient than when the two planes are directly adjacent, as indicated by Figure 5. Such a parallel location of planes dynamically improves the result. When the stack-up results in inefficient cancellation, Z-axis fields (ECM) may be developed, resulting in coupling within the circuit board in the same axis. Efficient choices for stack-ups can mitigate effects and improve performance for signal quality, S/N ratios and EMC performance.


Figure 3: Inefficient stack-up of planes for flux cancellation



Figure 4: Flux induction into vias implies series superimpositions of noise modulation


Figure 5: Efficient flux cancellation can null common-mode induction fields



Z-Axis Coupling With Respect To Packaging And Other Circuit Boards

When fields with related potentials are developed across the X-Y axis of circuit boards, the fields will couple to conductive chassis members or to other circuit boards located in close proximity. The coupling transfer functions may be described as: a) the equivalence equivalent of a distributed transmission line in the structure of a lattice, or b) a near-field effect, magnetic- field dominant, electromagnetic wave transfer.

Figure 6 describes these processes by illustrating a circuit-equivalent of the circuit board contribution to distributed line parameters.

As depicted in Figure 6, the patterned layout inductance circumscribing each IC circuit device becomes excited by the common-mode peak power currents, ICM. This results in a sequence of field potentials, E1 through E6, over the cross-section of the circuit board. Apart from the electrical field potentials that occur as a function of E = L di/dt (that cause E1 through E6), electromagnetic fields are developed. These fields propagate respectively from: a) the IC packages above the circuit board, b) the via holes acting locally as small loop antenna arrays, and c) the larger displacement patterns of the hole arrays created around the perimeters of the circuit devices.



Figure 6: Initial formation of distributed transmission line structure components derived from “pattern layout inductance” of a circuit board

It might be intuitively obvious that the structure of the distributed line is not adequately defined by a simple cross-section through a circuit board. In actuality, the distributed line is better considered as a lattice of three axes. The concept of this lattice is displayed in Figure 7.



Figure 7: Conceptual view of distributed transmission line components structured as a lattice in three axes


For clarity, the lattice structure is illustrated above the circuit board. It is important to note, however, that the distributed capacitance will present beneath the board in the distance separating the circuit board and the chassis plane. (It is also true, however, that if a conductive structure were placed above the circuit board, distributed capacitance would also be established across that dimensional separation.)

The initial concepts of a distributed transmission line may be observed in Figures 6 and 7 where it is noted both as current and common-mode fields transferred as a sequence action across the two boundaries of the distributed line (circuit board and chassis plane). When the distributed common-mode field potentials are formed (E1 through E6 across the cross-section of the circuit board), essentially any other conductive structure connected or coupled to the circuit board experiences common-mode derivative currents (I1 through I6) and potentials (ECM1 through ECM6) which are initially conveyed from the source board by distributed capacitance. This interaction can influence the signal-noise ratios among elements of the product by the propagation of these common-mode eddy currents across the distributed line. If considered as an electromagnetic wave transfer, it is noted that circuit boards (comprised of low power impedances with high spectral currents) will displace magnetic-field dominant near-field effects. Figure 8 suggests the equivalent wave impedance profiles that are exhibited in the coupling mechanisms of this mode of transfer.



Figure 8: Display of distributed transmission line with field potential map and common-mode current displacements


To gain a further concept of the potential coupling and interactions that are related to these common-mode transfers, Figure 9 is provided. The simple addition of two unshielded conductors (or cables) to opposing edges of the circuit board cross section immediately result in the development of several (approximately 5) antenna structures. These are: monopole A, monopole B, dipole C, circuit devices D (represented as an array), and slot structure E (established between the parallel planes). In this view, a dynamically active circuit board placed above a conductive plane with two connected wires or cables acts as a multi-mode interactive (and co-dependent) antenna array. This array is highly interactive with mutual noise influences (and intrinsic EMC issues within a system-product), as well as with related potentials and currents both across the circuit board and in connected wires and cables.



Figure 9: Interactive antenna structures can mutually cross-couple common-mode potentials

In order to further expand this discussion, the process of these transfers is related to the impedance and presence of electromagnetic waves that are propagating between the boundaries. For brevity, when an impedance that is initially formed through distributed capacitance becomes excited by electrical potentials, a current is formed across (through) the capacitance as a distributed electromagnetic coupling and transfer mechanism. The impedance of this electromagnetic wave transfer (ZW) is related to the magnitude of the electric field intensity divided by the current intensity. This essentially follows Ohm’s law, where a spatial term is added to provide a uniform standard
of dimension in the form of ZW = E-field intensity (in volts/meter)/H-field intensity (in amperes/meter). In practice, electromagnetic waves exist through various processes that alter the approximate impedance conditions of the wave. These processes are related to the distance of separation from the source of the wave to the point of observation. When this distance dimension is relatively close to the source, the wave condition is said to be in the near field. Electromagnetic waves that are observed in the near field condition tend to display either higher impedance conditions when in electric field dominance modes, or lower impedance conditions when in magnetic field dominance modes.

In order to establish a higher wave impedance electric field dominant condition, the conducted circuit nature of the electromagnetic wave source must possess in itself a higher voltage, higher impedance (hundreds to thousands of ohms) condition. For a lower impedance wave to be developed in the dimensions of the near field, the current conducted in the source must be of a low impedance, higher current nature. As applied to this discussion, it is noted that circuit boards are comprised of low power impedances (often in the low tens of ohms to below five ohms) with high spectral current amplitudes (amperes to tens of amperes of Ipp). By definition, circuit boards, by necessity of electrical characteristics, displace magnetic-field dominant, near-field wave impedance propagation effects. Figure 10 suggests the equivalent wave impedance profiles that are exhibited in the coupling mechanisms for this mode of transfer. These transfers are presented with respect to various packaging distances (separations between circuit boards and chassis as the “observation point” of the wave transfer), which extend to rather large lengths (> 50 cm).



Figure 10: Approximations of magnetic field dominant, near field, wave impedance


Utilizing the information presented in Figure 10, it is possible to visualize that the processes found across the distributed transmission line represented in lattice set up are (with very high probability) of a low impedance and intensely interactive nature. In practicality, it is reasonable to conclude that it is not possible to truly isolate a circuit board from a chassis structure, at least in terms of broad frequency spectral displacements. To attempt such isolation is to imply defiance of well-established, universally recognized electromagnetic wave processes! The logical inquiry is simply, “If isolation is not realistically possible, what are the alternatives?”

Control Of Common-Mode Transfers in the Z-Axis

With the recognitions suggested through the coupling concepts described, perhaps the most efficient common-mode Z-axis control stratagem starts with the recognition that the circuit boards are not isolated (i.e. cannot be isolated) from the conductive chassis!

Apart from efficiently designing the structures, energy storage and layout of the circuit boards themselves with an emphasis on reducing common-mode losses, efficient power delivery to circuit devices and high signal integrity, transfers from circuit boards to parallel conductive planes may be controlled using null techniques. These nulls are devised to set up deliberate reflections in the unintended, common-mode distributed transmission lines between circuit boards and chassis. Simply said, the idea is to deflect through reflections the circulation of common-mode levels toward regions of inefficient coupling, whereby signal-to-noise ratios (and EMC performance) may be optimized.

As with all intended reflection concepts, the magnitude of the intended reflection is found in the relationship of impedance values (and position) of the nulls compared to the impedance of the distributed line itself. Given the suggestions of impedance represented by Figure 10 (where wave impedance could approach the low tens of ohms) the impedance of nulls must be significantly lower (e.g., 1 ohm) in order to be effective. It is noted that, in concept, the method of implementing null reflections is similar to that of the intended impedance dichotomies found in shielding methods. In shielding theory, the impinging wave impedances are intentionally mismatched by the conductive shield impedance. The first effect of this mismatch causes the electromagnetic waves to be reflected off the shielding surface and away from the area to be protected from the potentially offending amplitudes conveyed by the wave.

The process of reflected null implementation is exhibited in concept by Figure 11. The intention of this technique is to redirect the common-mode transfers to improve signal-to-noise and all effects related to Z-axis coupling. Note that a null is essentially a connection between logic return (L0) and chassis through a low impedance means (e.g., through a short, conductive, circuit board mounting standoff). Nulls shunt the potentials developed across the two planes of the distributed transmission line and reflect the common-mode Z-axis levels away from the null positions. Although in low spectral common-mode distributions (e.g., greater than 500 MHz) nulls may be effective at or as an array of specific locations, much higher frequency common-mode spectra may require the use of null bars (continuous strips) of contiguous regional contact to prevent slot aperture formations at short wavelengths. (Short aperture slot formations may inadvertently become efficient antenna structures.)


Figure 11: Common-mode potentials redirected as intentional eddy currents through reflective null mismatches within impedance flow of distributed line (wave transfer impedance)


Another effect may be observed in the process represented by Figure 11. The common-mode potentials developed across the circuit board are being partially shunted by the common-mode impedance of the chassis plane.

From this observation, it is possible to conclude that the common-mode performance of the circuit board itself must be improved. A caution is appropriate to note in utilizing these techniques: the null formations establish intended common-mode eddy currents. Those common-mode currents circulate in a pattern across the surface of the chassis plane and back up through the circuit board. The conclusion yielded from this observation is that caution must be used in locating the nulls so that the intended (redirected) common-mode currents will protect, not invade, sensitive circuit regions.

With appropriate implementation, it is indeed possible to improve common-mode performance utilizing the techniques represented. Performance improvement includes increasing signal-to-noise performance (particularly across sensitive partitions) and, accordingly, the EMC within the system-product itself. favicon

This article was originally prepared for The University of Oxford.

author_king-wmichael W. Michael King
is a systems design advisor who has been active in the development of over 1,000 system-product designs in a 50 year career. He serves an international client base as an independent design advisor. Many terms used for PC Board Layout, such as the “3-W Rule”, the “V-plane Undercut Rule”, and “ground stitching nulls”, were all originated by himself. His full biography may be seen through his web site:, he is the author of EMCT: High Speed Design Tutorial (ISBN 0-7381-3340-X) which is the source of some of the graphics used in this presentation. EMCT is available through Elliott Laboratories/NTS, co-branded with the IEEE Standards Information Network.



About The Author

W. Michael King

W. Michael King is a systems design advisor who has been active in the development of over 1,000 system-product designs in a 50 year career. He serves an international client base as an independent design advisor. Many terms used for PC Board Layout, such as the “3-W Rule”, the “V-plane Undercut Rule”, and “ground stitching nulls”, were all originated by himself. His full biography may be seen through his web site: Significantly, he is the author of EMCT: High Speed Design Tutorial (ISBN 0-7381-3340-X) which is the source of some of the graphics used in this presentation. EMCT is available through Elliott Laboratories/NTS, co-branded with the IEEE Standards Information Network.

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