Capacitance

This article provides practical guidance on the implementation of the SEMI E176 standard for managing EMI in a semiconductor manufacturing environment and device handling such as printed circuit board assembly.

In this article, the author will identify two major types of single-conductor structure resonances and describe some case studies for both. He will then describe how design projects can quickly and easily be ‘de-risked’ from the possibilities of suffering either type of resonance by the use of low-cost field and circuit simulators and/or low-cost bench testing on physical ‘mock-ups’.

TLP ideas are helpful in understanding CDE, but it is an imperfect analogy

ESD models may be used for simulating on-chip integrated circuits or system (board) level circuits with discrete electronic components like diodes, TVS devices, and bipolar junction transistors (BJTs).

This article examines the different parts of capacitive touch design and provides a checklist of what to look for when designing a product.