hot topics in esd Archives - Page 2 of 5

Latch-up Electronic Design Automation Checks

This article introduces typical latch-up verification techniques to detect and prevent latch-up. These techniques rely on electronic design automation (EDA) tools to deliver the coverage necessary to identify and eliminate latch-up risks.

ESD in Joe’s Garage

When handling ESD-sensitive components, we must protect them from ESD damage.

Indium-gallium-zinc-oxide (IGZO) Thin-film-transistors (TFT) and ESD

The thin-film transistor (TFT) became commercially available slightly more than 30 years ago in the form of a switch for the Liquid Crystal Display.

Characterization for ESD Design, the TLP Zoo: Part 2

This is the second of a two-part series on transmission line pulse (TLP) testing.

Characterization for ESD Design, the TLP Zoo: Part 1

Author’s Note: This is the first of a two-part series on the TLP Zoo, the variety of transmission line pulse (TLP) systems used in the characterization of electrical components and system of ESD robustness. In ... Read More...

What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.

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