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The Transistor: An Indispensable ESD Protection Device – Part 1

Use of Bipolar Transistor ESD Protection in RF Technologies

Since its invention in 1947 at Bell Labs by William Shockley, Walter Brattain, and John Bardeen, the bipolar transistor has been implemented in multiple key applications successfully. Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products. For on-chip electrostatic discharge (ESD) protection solution, the bipolar junction transistor, represented in Figure 1, is a very effective and valuable ESD device. With high ESD performance, low leakage, low input capacitance, and compactness, it has a smaller footprint advantage compared to other ESD devices. Furthermore, modern bipolar devices are reaching record RF performance including but not limited to a high transition frequency fT > 300GHz and minimum noise figure NFMIN < 1dB.

Figure 1: A simplified cross-section of the bipolar junction transistor. Inset is its electrical symbol [1]

The NPN device can be implemented as a very effective standalone primary ESD protection for pad-based ESD protected input/output in RF and high-speed applications especially. The trigger voltage of the latch-back silicon junction bipolar NPN transistor is very much dependent on the base-emitter discrete resistor RLB value (Table 1). The latter must be chosen and tuned according to the device to be protected in the core of the integrated circuit and the so‑called ESD design window.

Device Parameters Triggering Parameters Holding Parameters Failure Parameters
Device RLB[kW] VT1[V] IT1[mA] VON[V] RON[W] VT2[V] IT2[A]
NPN_Rlb_10k 10 8.9 1.0 3.4 2.3 6.1 1.1
NPN_Rlb_100k 100 4.8 1.0 3.4 2.3 6.1 1.1
NPN_Rlb_1M 1000 4.4 1.0 3.4 2.3 6.1 1.1

Table 1: ESD parameters of an example standalone latch-back bipolar NPN transistor

In this example, the standalone latch-back bipolar NPN transistor can withstand up to 1.1A transmission line pulse (100ns-TLP), this is equivalent to about 2kV human body model (HBM) robustness in terms of energy content as shown in Figure 2.

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Figure 2: 100ns-TLP measurements of a latch-back bipolar NPN transistor. Inset shows its typical implementation between two pads.

Using MOS Transistors as ESD Protection Clamps in CMOS Circuits

Since the beginning of ESD protection design, MOSFET transistors are common ESD protection devices in CMOS circuits. The ESD current is discharged either through the MOS-channel in a power clamp or conducted by the parasitic bipolar transistor that is inherent in every MOS transistor. Figure 3 shows the simplified schematics for both ESD clamp concepts.

Figure 3: Use of MOS transistors as ESD clamps: principle schematics of a NMOS based power clamp (a) and grounded-gate NMOS based IO protection (b)

In a power clamp, a transient trigger circuit biases the gate of the “big MOS transistor” for the duration of the ESD current. The MOS-channel provides the low-ohmic path to ground. During normal operation, the trigger circuit keeps the gate closed and the ESD clamp off. In a grounded-gate configuration for a MOS transistor, a high value resistor connects gate, source and bulk. This prevents the biasing of the gate and opening of the MOS channel during ESD stress and normal operation. However, during ESD stress the parasitic bipolar transistor between drain and source (Figure 4) turns on and provides a path to ground for the conduction of the ESD current.

Figure 4: Cross-section of a NMOS transistor in grounded-gate configuration. The parasitic bipolar is here a NPN with the drain as collector, the source as emitter and the bulk as base.

Continuous technology scaling increases the contact resistance. This led to the introduction of silicidation from the 0.35 µm CMOS process node. Silicides are low-ohmic films in the active areas of transistors. Because of the high currents during ESD stress, silicidation has a negative impact on the ESD robustness of MOS transistor based ESD clamps. Silicidation leads to a non-uniform current conduction in the drain and source areas. In fully silicided MOS devices, the ESD current concentrates close to the gate. This locally increases the current density and reduces the failure level of the device. A silicide-blocking mask between drain and gate (Figure 5) helps to reduce this “current crowding effect” and enables a uniform spread of the current. The ESD design measure enables a significant improvement of the failure current during ESD stress (Figure 6).

Figure 5: Device cross-section and simplified layout view of a fully silicide grounded-gate PMOS transistor (a) and a silicide block grounded-gate PMOS with silicide-blocking (SB) between drain and gate (b)


Figure 6: Comparison of 100ns TLP-IV curves of a fully silicide grounded-gate PMOS and a silicide block grounded-gate PMOS: complete TLP IV curves (a) and zoom-in to failure of the fully silicide device (b)


As described in this article the invention of the bipolar transistor has seen the technology evolve into wide semiconductor applications. Both the bipolar transistor and MOS transistor continue to provide effective ESD protection options. 


  1. Dolphin Abessolo-Bidzo et al., “A Silicon BJT Active ESD Clamp Design in a Silicon Germanium HBT BiCMOS Technology,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, paper 4A.1, 2021.

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