hot topics in esd

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.

Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has...

Historical Background  CDM is an important model for ESD qualification. The well-known CDM refers to...

Human Body Model (HBM) is the original ESD test method for semiconductor devices and...

This article reviews some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.

Optical communication can dramatically increase the bandwidth between servers while reducing complexity, power consumption, and cost.

In the past six months, EOS/ESD Association, Inc. released eight new or revised documents on electrical overstress (EOS), grounding, packaging materials, seating (chairs), footwear, hand tools, gloves, and human metal model.

With the advent of wide-spread wireless electronics, the need for high-performance RF components to be built into highly reliable and robust products continues to expand.