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ESD Challenges in 2.5D/3D Integration

Introduction

2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package. Back in the 1990s IC dies were placed next to each other and connected through wire bonding. Later in the 2000s this was also applied to three-dimensional die stacking. Since the 2010s the industry has been  working on IC packaging where vertical stacked dies are connected through embedded Through-Silicon-Via (TSV) and micro-bumps or hybrid bonding. In 2.5D ICs the dies are placed next to each other and connected through an interposer. In 3D ICs the dies are vertically stacked and TSVs and die-to-die interfaces are used to connect the single dies.

ESD Challenges in 2D/3D ICs

Electro-Static Discharges (ESD) can occur during die or wafer stacking. Die pick-up, die transfer and die or wafer bonding (Figure 1) are process steps with an increased risk for ESD. Like for conventional IC packaging ESD control and ESD protection design are available to prevent ESD related damages. ESD control techniques minimize the charging and discharging during the stacking and bonding process. Protection design increases the ESD robustness of die-to-die interfaces.

Figure 1: ESD risks in a die-to-wafer bonding process [1]

The manufacturing of commercial 2.5D and 3D ICs has specific ESD related challenges that need to be solved. Typically, there are a very large number of die-to-die interfaces and small bump pitches. It is expected that the number of die-to-die interfaces in 3D ICs will increase further. Figure 2 shows a roadmap for the coming years.

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Figure 2: Industry council roadmap for number of die-to-die interfaces per 3D IC package and expected CDM withstand voltages [1]

The large number of interfaces leaves no or only little area for an ESD protection design of every die-to-die IO. Instead, very often a self-protecting approach must be used together with sufficient ESD control measures. Two scenarios can be assumed. If the stacking and bonding is done in-house the 3D IC manufacturer has control over all process steps. A very good ESD control and a self-protecting only approach for the die-to-die IOs is possible. If the stacking and bonding is done by an external supplier, the ESD control may follow only the requirements of S20.20. Some ESD protection design for the die-to-die IOs might be necessary.

Both approaches require extracting the intrinsic ESD robustness of the die-to-die IOs. ESD testing methods are needed that can test reliable with low stress level, low variability. Also, they must be capable of  applying the stress to bare dies. Contact CDM testing methods like Charge-Coupled TLP (cc‑TLP, [2]) and Low-impedance Contact Charge Device Model (LICCDM, [3]) are examples for suitable ESD testing methods.

ESD verification of a 3D IC products designs provide another challenge because of the large number of die-to-die interfaces and possible metal routing across different dies. To enable a reliable ESD verification for these types of products it is required to use advanced Electronics Design Automation (EDA) tools, new verification approaches and to deal with high computing power requirements.

Outlook

There is a lot of on-going research and development work to further improve the ESD control and to better understand the electrostatic effects during the bonding process. To support the industry in this effort the Industry Council will soon publish a white paper that provides guidance on ESD target levels, on ESD testing of die-to-die interfaces and for IP development in 2.5D and 3D ICs. 

References

  1. M. Simicic, M. Scholz, “ESD Challenges in 2.5D/3D Integration“, India ESD Forum 2022.
  2. Industry Council on Target Levels (Whitepaper 2), May 2021.
  3. H. Wolf, H. Gieser, W. Stadler, and W. Wilkening, “Capacitively coupled transmission line pulsing CC-TLP – A traceable and reproducible stress method in the CDM-domain,” EOS/ESD Symposium, 2003.
  4. N. Jack, T.J. Maloney, B. Chou, E. Rosenbaum, “WCDM2 – Wafer-level charged device model testing with high repeatability,” Reliability Physics Symposium (IRPS), 2011.

Dr. Mirko Scholz, Infineon Technologies AG, received his Ph.D. in Electrical Engineering from the Vrije Universiteit in Brussels (VUB). He has authored/co-authored more than 100 publications, tutorials, and patents in the field of ESD design and testing. He is a regular reviewer for several IEEE journals and a current member of the IRPS sub-committee on ESD and Latchup.

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Marko Simicic joined the ESD team at imec in Belgium in 2017 with the focus on researching ESD solutions for devices and circuits. He has authored or co-authored more than 35 papers in international journals and conference proceedings and is an active member of the JS-002 ANSI/ESDA/JEDEC joint standard for CDM ESD device sensitivity testing.

 

 

 

 

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