The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.
In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.
Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but ... Read More...
Historical Background CDM is an important model for ESD qualification. The well-known CDM refers to the discharge of an IC package to a grounded surface, whether from automatic handlers in a production area o... Read More...
This article reviews some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.
Optical communication can dramatically increase the bandwidth between servers while reducing complexity, power consumption, and cost.
In the past six months, EOS/ESD Association, Inc. released eight new or revised documents on electrical overstress (EOS), grounding, packaging materials, seating (chairs), footwear, hand tools, gloves, and human metal model.
With the advent of wide-spread wireless electronics, the need for high-performance RF components to be built into highly reliable and robust products continues to expand.
Let’s look at how a static control flooring system is intended to function. The flooring systems’ purpose is to provide an electrical path, typically to ground, for personnel when used in conjunction with static control footwear, for removal (equalization) of electrostatic charge.