Updated Trends in Charge Device Model (CDM)
As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.
Challenges of Designing System-level ESD Protection at the IC Level, Part 2
It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).
ESD Challenges in 2.5D/3D Integration
2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.
A Look Into Generator Waveforms: Do They Meet the IEC 61000-4-2 Waveform Specification?
This article explores the waveform specifications called out in the IEC 61000-4-2 standard.
The Transistor: An Indispensable ESD Protection Device – Part 1
Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products.
Commercial Versus Automotive ESD Integrated Circuit Qualification: Part 2
This is Part 2 of an article describing the difference between the electrostatic discharge (ESD) qualification requirements for automotive and standard commercial integrated circuits.
Commercial Versus Automotive ESD Integrated Circuit Qualification, Part 1
Integrated circuits intended for automotive applications have higher electrostatic discharge (ESD) qualification requirements than those intended for commercial and consumer electronics.
Industry Council’s Latch‑up Survey
This article provides a high-level overview of the Industry Council paper “Survey on Latch‑up Testing Practices and Recommendations for Improvements,” which describes the full analysis of the collected responses and lays a path for potential adaptations needed to accommodate its use in future technologies and applications.
Latch-up Electronic Design Automation Checks
This article introduces typical latch-up verification techniques to detect and prevent latch-up. These techniques rely on electronic design automation (EDA) tools to deliver the coverage necessary to identify and eliminate latch-up risks.
ESD in Joe’s Garage
When handling ESD-sensitive components, we must protect them from ESD damage.