hot topics in esd

This article introduces typical latch-up verification techniques to detect and prevent latch-up. These techniques rely on electronic design automation (EDA) tools to deliver the coverage necessary to identify and eliminate latch-up risks. 

When handling ESD-sensitive components, we must protect them from ESD damage.

The thin-film transistor (TFT) became commercially available slightly more than 30 years ago in the form of a switch for the Liquid Crystal Display.

This is the second of a two-part series on transmission line pulse (TLP) testing.

Author’s Note: This is the first of a two-part series on the TLP Zoo,...

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.

Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has...

Historical Background  CDM is an important model for ESD qualification. The well-known CDM refers to...