Columns

This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

This article introduces typical latch-up verification techniques to detect and prevent latch-up. These techniques rely on electronic design automation (EDA) tools to deliver the coverage necessary to identify and eliminate latch-up risks. 

This year, 2022, is a revision cycle year for ANSI Z535, and it marks the first time many of the standards have changed in over a decade. This month’s column explores the latest updates and what they mean for product safety.

Search and rescue transmitter interferes with car alarms, central locking, and garage door openers in Las Vegas.

This is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

When handling ESD-sensitive components, we must protect them from ESD damage.

Walkie-talkies interfere with electronic door locks on aircraft cockpits.

This is the first of three articles devoted to the design, test, and electromagnetic compatibility (EMC) immunity evaluation of multilayer PCBs containing analog circuitry. In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques.

Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.

This article presents a simple method of estimating the parasitics of the three passive circuit components (R, L, C).