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Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors, Part 3

Via placement and trace geometry significantly affect decoupling capacitor performance. This final installment of a three-part series presents conducted emissions measurements across six PCB via topologies, revealing how distance from the power-ground plane pair and via spacing impact EMC results.

Common Pitfalls with ESD Flooring Systems

ESD flooring systems fail more often from misunderstanding than bad materials. This article walks through nine common pitfalls — from confusing anti-static with ESD-safe to poor grounding and installation shortcuts — and how to avoid each one.

Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors, Part 2

Conducted emissions testing on custom PCBs shows how moving a decoupling capacitor farther from an IC can increase emissions across multiple frequency bands. Using CISPR 25 methods, this study compares capacitor placements and via topologies to reveal how distance and inductance shape PDN behavior.

Small Form Factor CDM Testing, Part 3

Small form factor devices often fail traditional field‑induced CDM testing, prompting the need for contact‑first methods. This article compares CC‑TLP, low‑impedance contact CDM, and relay‑based CDM techniques, outlining how each provides more repeatable, lower‑noise stress conditions for bare die and wafer‑level testing.

Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors, Part 1

Explore how PCB via and trace geometry influence the real‑world effectiveness of decoupling capacitors. This first article in the series defines six board variants, capacitor placement strategies, and PCB topologies, setting the stage for upcoming RF emission results based on CISPR 25 testing.
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Small Form Factor CDM Testing, Part 2

This column explores two air‑discharge‑based methods for testing small form factor products under the Charged Device Model. It examines limitations of traditional FICDM testers, presents wafer‑level and bare‑die testing approaches, and introduces contact‑first CDM techniques designed to improve reliability for fine‑pitch and low‑voltage devices.

Shielding to Prevent Radiation: Part 7

Even perfect shields fail with poor aperture design. Learn how slot orientation, size, and placement affect shielding effectiveness, and discover why multiple small holes outperform single large openings using Babinet's principle.

Small Form Factor CDM Testing: Part 1

FICDM testing wasn't designed for today's tiny chiplets and flip chip assemblies. Part 1 explores critical challenges: probes too large for microbumps, unreliable air discharge below 250V, and the mounting dilemma for bare die products.

Shielding to Prevent Radiation, Part 6

Understanding how shields perform in the near field requires accounting for wave impedance differences between electric and magnetic sources. This sixth installment derives shielding effectiveness formulas for near-field conditions and reveals a surprising truth: copper outperforms steel at low frequencies, but steel's superior absorption reverses this advantage above 4kHz.

Can Mechanical Movements on FI‑CDM Tester Cause Additional Zap During CDM Stress?

Secondary discharges during Field-Induced CDM testing aren't just measurement anomalies—they're real stress events caused by mechanical bouncing of the pogo pin. This groundbreaking investigation reveals how contact vibrations trigger unintended zaps with opposite polarity, provides electrical proof of the mechanism, and offers practical solutions to prevent this hidden reliability threat.
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