Absence of IC ESD Sensitivity Data Has Reached a Critical Stage

ESD sensitivity data is not readily available to the public from IC suppliers to determine if a company’s ESD control program can handle its components.  A recent review of publicly available datasheets revealed that an estimated 70% of datasheets included HBM withstand voltages and an estimated 10% included CDM sensitivities. This is creating a serious problem that is escalating rapidly with technology advancements as discussed further in Section 3.0. It is essential to know when component sensitivities fall below manufacturing capability levels. Both manufacturing and board level design teams need this information in a timely manner to avoid quality and reliability excursions.

EOS/ESD Association, Inc. Initiative

The absence of device ESD sensitivities in the public domain has reached a critical stage as demonstrated through IC threshold trends and in the case study discussed in this article. EOS/ESD Association, Inc. (ESDA) started an initiative to encourage IC suppliers to make the data readily available. ESDA formed a small group of industry leaders to evaluate and recommend actions to address the lack of data concern. This article is one of the actions aimed at educating the industry, including IC suppliers, of the importance of making device ESD sensitivities available in the public domain. Another action was the development of a new standard practice by ESDA’s standards working group WG5.0 – Device Testing. The final document is expected to be released in late 2018/early 2019 and will be designated “ANSI/ESD SP5.0-2018 – Reporting ESD Withstand Levels on Data Sheets.” This document was written by industry experts with the intent to provide IC suppliers with guidelines that could be used to publish the data and a common representation of the information so that device users know what to expect. Other standards device testing working groups are looking into the possibility of adding requirements for manufacturers to have a process for obtaining ESD device sensitivity data. The ESDA/JEDEC joint working groups for HBM and CDM standards are considering a statement that would strongly recommend that publicly available product datasheets report minimum CDM and HBM sensitivities.

IC Device Threshold Trends

This section is a reproduction (with some modification) of the ESD Technology Roadmap [1].

The requirements for increased performance (devices that operate at 1 GHz and higher) and the increase in the density of circuits (Moore’s Law) on a device caused problems for traditional ESD protection circuits. This has been exacerbated with the continued scaling of the technologies toward sub-22 nm feature sizes in order to achieve higher density and performance. As a result, both human body model (HBM) and charged device model (CDM) target levels had to be lowered to accommodate these features. Also, radio frequency (RF) circuit operations will continue their growth, with these pins only tolerating a very low capacitive load from ESD cells. Due to these trends, ICs are expected to become even more sensitive to ESD events in the years 2020 and beyond. Therefore, it is anticipated that the prevailing trend will continue in this manner for meeting increased circuit performance demands at the expense of the designed ESD protection levels.

EOS/ESD Association, Inc. Device ESD Threshold Roadmaps

The following graphs show the device ESD design sensitivity trends based on the most relevant and important ESD models used by device manufacturers as part of the device qualification process: HBM and CDM. The sensitivity limits are a projection by engineers from leading semiconductor manufacturers.

Human Body Model (HBM) Roadmap

The projections for HBM design (typical min and max) are indicated in Figure 1. Although design improvements were made from 1978 through 1993, representing a learning curve process, advanced circuit performance effects started to take place around this time, eventually degrading the levels. The max levels represent what is typically possible from technology scaling for designs without the high-speed circuit performance requirements, and min levels represent the constriction coming from designs needing to meet the high-speed circuit performance demands.

ESDA Charged Device Model (CDM) Roadmap

The technology impact on CDM not only comes from the required IO speeds but also from package size effects. Larger packages will experience higher discharge currents at a given stress voltage level. Although the chart does not cover all IC package types, Figure 2 illustrates the combined IO design and package effect as projected for a 22 nm technology node. The color scheme adopted in Figure 2 is based on the validation that 250 volts CDM is safe for production areas [2]. This map would change as the technology is further scaled or package sizes become even larger. For example, note that for today’s packages of 3000 pins (~3000-3500 mm²) or more (not uncommon for a microprocessor) in a land grid array (LGA) or ball grid array (BGA), high speed IOs at the 22 nm node would barely meet a CDM target level of 125 volts. An additional package effect, decreasing thickness, was not included here for simplicity. In the figure, the current values indicated for each type of IO design represent the maximum withstand current value for meeting the performance constraints at the I/O based on the particular IO design. These design current values are then translated into CDM voltage levels that are possible to meet depending on the package size variations.

Based on the above, the projections for CDM sensitivity levels (typical min and max) are indicated in Figure 3. As shown in the figure, the CDM target has been modified to 250 volts, reduced from the previous 500 volts. But a target of 125 volts will be realistically needed in the future.

A closer observation Figure 3 might suggest that as we look ahead to 2020, there will really be no significant change in the typical range for CDM sensitivity limits. While the belief is that the range may not change dramatically by 2020, the distribution of products within this range may vary with a change in the mix of companies remaining on today’s traditional technologies and those who continue to push for technology advancements through the need for higher performance devices and growth in package size/complexity through multichip packages such as 2.5D and 3D [3, 4]. Figure 4 is a first look into how this distribution of products could conceivably look by 2020. The bottom two groups for CDM distributions are of higher concern. Thus, the industry needs to be better prepared for a relatively larger population of sensitive CDM devices by the year 2020.

Case Study: Circuit Board Manufacturing Stoppage due to Lack of ESD Sensitivity Data [5]

A new circuit board design was introduced to manufacturing without device ESD sensitivity data. As a result, manufacturing was unaware that a high-speed device on the board had a 15 V CDM sensitivity, which is well below the scope of ANSI/ESD S20.20. The result was extreme fluctuations in circuit board assembly yields (Figure 5) during ramp up of a one-billion-dollar product line. Between the months of June and September, the removal rate varied dramatically between 10 and 30 percent. In actual lot-to-lot observation, some lots showed 100-percent drop out.

Due to the high failure rate of these devices, the cost implications were very high. Therefore, a detailed investigation was undertaken. Through failure analysis, it was confirmed that the devices were failing due to ESD damage. A special detailed audit was conducted, and a team of people experienced in different aspects of the issue were consulted. An assessment of the manufacturing line was undertaken and corrective actions aimed at general improvements of the existing ESD control process were compiled. Based on that action plan, a task force was assembled and assigned to correct deficiencies in the line and to provide status reports weekly to executives. Because of the extreme seriousness of this situation, the weekly reports were channeled to high-level executives in the company.

Initially, many special handling precautions were added or enhanced (Table 1) totaling over $300,000. Yet, even with this special attention and with the fullest compliance with the procedures, yields continued to fluctuate dramatically from June through September (Figure 5).

Table 1: Added or Enhanced Special Handling Precautions Totaling over $300K

The solution to this problem was found in the introduction of a customized “shunt” which consisted of a static dissipative foam cover for the device configured to tie all device leads together. The shunt was placed on top of a device immediately after the solder reflow oven where it remained until electrical test. The yields improved dramatically and approached 98%.

The simplicity of this solution is particularly striking in contrast to more complex and costly alternatives. The incremental cost for the shunt was $1,000. The annual dollar savings realized on the production line reached $6.2 million per year for this one device on this one line.

One additional benefit derived from this case was the impact that it had on the design community. Asked to justify a withstand voltage of 10 volts CDM, designers responded by redesigning the device and raising the level of sensitivity to 750 volts HBM and 100 volts CDM, a remarkable accomplishment. Board level design changes were made to accommodate the capacitive load from the new protection circuitry and maintain the system performance.

If the device sensitivity had been known prior to initial production, this crisis could have been averted. The device could have been redesigned and/or it would have been possible to anticipate the challenges in production. A more orderly set of counter measures could have been phased in, evaluated and refined without the extraordinary time sensitive pressure during ramp up of a billion-dollar product line.

Conclusion

With the downward trend in IC ESD thresholds as discussed, it is essential to know, prior to initial production, when component sensitivities fall outside the scope of the document. The absence of device ESD sensitivity data in the public domain has reached a critical stage and will only worsen with technology trends towards the expanding use of extreme ESD sensitivities. Therefore, it is strongly recommended that manufacturing quality executives require notification of any such devices to avoid a production crisis such as the case study described above. Likewise, it is strongly recommended that IC suppliers make the data readily available either in publicly available data sheets utilizing the standard practice being developed by EOS/ESD Association, Inc. or in other documentation in the case of custom devices.

References

1. ESD Technology Roadmap; https://www.esda.org/standards/complimentary-downloads/view/1869.
2. Industry Council on ESD Targets, White Paper 2: “A Case for Lowering Component Level CDM ESD Specifications and Requirements,” March 2009, http://www.esda.org/white-papers.
3. Global Semiconductor Alliance, “Electrostatic Discharge (ESD) in 3D-IC Packages”, Version 1.0, January 2015, http://www.gsaglobal.org/working-groups/3d-ic-packaging.
4. Nagata, M.; Takaya, S.; Ikeda, H.; Linten, D.; Scholz, M.; Chen, S.; Hasegawa, K.; Shintani, T. and Sawada, M. ‘CDM protection of a 3D TSV memory IC with a 100 GB/s Wide I/O data bus’, Proceedings EOS/ESD Symposium, 2014, p. 61 – 67.
5. ISBN 0-412-13671-6, G. Theodore Dangelmayer, ESD Program Management, 2nd Edition, p 63, 1999.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

Ted Dangelmayer is the president of Dangelmayer Associates, LLC and has assembled an ESD consulting team consisting of the foremost authorities in virtually all ESD areas of both product design and manufacturing. He received the “Outstanding Contribution” award and the EOS/ESD Association, Inc. “Founders” award. He was president of EOS/ESD Association, Inc., chairman of the ESDA standards committee, and general chairman of the EOS/ESD Symposium. He has published two editions of his book, ESD Program Management, numerous magazine articles, and technical papers. Ted holds three patents and is iNARTE certified. He is currently president of the Northeast local chapter of EOS/ESD Association, Inc., a member of the ESDA education Council, ESDA Marketing Team, Advanced Technologies Team and ESDA Publicity Team.