What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

Use of HBM and CDM Layout Simulation Tools

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

What Are the Advantages of Capacitively Coupled TLP (CC-TLP)?

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

Next to FinFET, How Will ESD Suffer?

Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.

What Exactly is ESD for 3D ICs?

The EOS/ESD Association is addressing the various vectors of development needed to support 3D packaging ESD integration and manufacturing ESD control.