In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.
Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.
Our knowledge of ESD and how to control it has grown significantly over the past 50 years. This article maps the history of that journey.
The EOS/ESD Association is addressing the various vectors of development needed to support 3D packaging ESD integration and manufacturing ESD control.
Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but ... Read More...
Historical Background CDM is an important model for ESD qualification. The well-known CDM refers to the discharge of an IC package to a grounded surface, whether from automatic handlers in a production area o... Read More...
As innovation comes from many sources, it is difficult to predict or accurately forecast future display technology development. Curved and flexible displays were introduced as the most innovative display technology achievement along with OLEDs in the last 10 years.
How is the proper ESD Protection Cell chosen for a particular design application?
The purpose of AMR is to warn “customers” who use the semiconductor product that there are physical limits that must not be violated if reliability is to be preserved.
This article reviews some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.