ESD in Joe’s Garage
When handling ESD-sensitive components, we must protect them from ESD damage.
Low Voltage Charged Device Model (CDM) Testing at a Crossroads
Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.
Indium-gallium-zinc-oxide (IGZO) Thin-film-transistors (TFT) and ESD
The thin-film transistor (TFT) became commercially available slightly more than 30 years ago in the form of a switch for the Liquid Crystal Display.
Characterization for ESD Design, the TLP Zoo: Part 2
This is the second of a two-part series on transmission line pulse (TLP) testing.
Characterization for ESD Design, the TLP Zoo: Part 1
Author’s Note: This is the first of a two-part series on the TLP Zoo, the variety of transmission line pulse (TLP) systems used in the characterization of electrical components and system of ESD robustness. In ... Read More...
What Are External Latch-up and Internal Latch-up?
Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.
Use of HBM and CDM Layout Simulation Tools
The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.
Understanding Footwear and Flooring in ESD Control
If you really want to know whether your footwear and flooring are working together, measure the resistance from the wearer via footwear and flooring to earth (ground).
What Are the Advantages of Capacitively Coupled TLP (CC-TLP)?
Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.
Automated Latch-Up Verification in 2.5D/3D ICs
In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.