EOS/ESD Association, Inc.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

From This Author

Small Form Factor CDM Testing: Part 1

FICDM testing wasn't designed for today's tiny chiplets and flip chip assemblies. Part 1 explores critical challenges: probes too large for microbumps, unreliable air discharge below 250V, and the mounting dilemma for bare die products.

Can Mechanical Movements on FI‑CDM Tester Cause Additional Zap During CDM Stress?

Secondary discharges during Field-Induced CDM testing aren't just measurement anomalies—they're real stress events caused by mechanical bouncing of the pogo pin. This groundbreaking investigation reveals how contact vibrations trigger unintended zaps with opposite polarity, provides electrical proof of the mechanism, and offers practical solutions to prevent this hidden reliability threat.

How TVS Properties and Printed Circuit Board Design Influence Peak Voltage and Residual Current at an IC for USB-C SuperSpeed Data Lines

USB-C's high-speed data lines need robust ESD protection, but TVS device placement matters critically. New research reveals why positioning protection behind AC coupling capacitors—not in front—delivers superior IC protection for sensitive SuperSpeed applications.

Addressing an Industry Concern: The Demand for a CDM Bare Die Testing Method

Traditional Charged Device Model testing falls short for bare dies in 2.5D/3D devices. With discharge currents reaching 500 mA at just 5V, existing methods can't handle the unique challenges of testing unpackaged components. CCTLP emerges as a promising alternative for reliable low-voltage testing.

Why ESD Electronic Design Automation Checks are So Critical: Part 1

This article introduces an upcoming Technical Report (TR18) from the ESD Association on Electronic Design Automation checks. It details integrated ESD verification throughout IC design phases, covering schematic-based topological checks and layout-based verification to ensure comprehensive ESD protection in modern circuits.
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AC and DC Ionization, the Whole Story

The teaser maintains a technical, authoritative tone that should appeal to engineering professionals while highlighting the article's key experimental findings. It addresses the misconceptions about AC ionizer safety and emphasizes the quantitative approach taken in the study, which should generate interest among readers concerned with ESD protection in semiconductor manufacturing environments.

An Overview of ANSI/ESD S20.20 – The Cornerstone of Semiconductor Control Programs

The ANSI/ESD S20.20 standard has become the cornerstone for developing effective ESD control programs. This standard is essential for safeguarding sensitive electronic components and minimizing failure rates.

SOIC & SOT: The Microchips: Engineers Choose the Ten Best STEM Toys to Gift

Purdue University's Engineering Education College has selected "SOIC and SOT" as the #1 children's book on its pre-engineering STEM gift-giving guide.

The Impact on ESD Risk of AI on Silicon Fabrication and the Implications of Increasing Memory Stacks

This column explores the significant impact of artificial intelligence on advancements in silicon fabrication, focusing on the development of high bandwidth memory (HBM) and associated die-to-die(D2D) electrostatic discharge (ESD) protection challenges.

Machine Learning Applications in the Novel ESD Compact Modeling Methodology

This column explores the application of machine learning techniques in ESD compact modeling for semiconductor devices. It compares traditional methods with a new machine learning approach, highlighting improved efficiency and accuracy in predicting ESD protection performance.
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