Columns

Before you can calculate shielding effectiveness, you need to know whether your material qualifies as a good conductor — and that's where loss tangent comes in. This deep dive connects the math to the physics, from plane wave propagation to practical near- and far-field shielding formulas.

Grounding is the foundation of any ESD control program — but doing it right means more than just connecting a wrist strap. This primer covers the key requirements of ANSI/ESD S20.20, common grounding techniques, and what's coming in the next revision of S6.1.

Via placement and trace geometry significantly affect decoupling capacitor performance. This final installment of a three-part series presents conducted emissions measurements across six PCB via topologies, revealing how distance from the power-ground plane pair and via spacing impact EMC results.

ESD flooring systems fail more often from misunderstanding than bad materials. This article walks through nine common pitfalls — from confusing anti-static with ESD-safe to poor grounding and installation shortcuts — and how to avoid each one.

Conducted emissions testing on custom PCBs shows how moving a decoupling capacitor farther from an IC can increase emissions across multiple frequency bands. Using CISPR 25 methods, this study compares capacitor placements and via topologies to reveal how distance and inductance shape PDN behavior.

Small form factor devices often fail traditional field‑induced CDM testing, prompting the need for contact‑first methods. This article compares CC‑TLP, low‑impedance contact CDM, and relay‑based CDM techniques, outlining how each provides more repeatable, lower‑noise stress conditions for bare die and wafer‑level testing.

Explore how PCB via and trace geometry influence the real‑world effectiveness of decoupling capacitors. This first article in the series defines six board variants, capacitor placement strategies, and PCB topologies, setting the stage for upcoming RF emission results based on CISPR 25 testing.

This column explores two air‑discharge‑based methods for testing small form factor products under the Charged Device Model. It examines limitations of traditional FICDM testers, presents wafer‑level and bare‑die testing approaches, and introduces contact‑first CDM techniques designed to improve reliability for fine‑pitch and low‑voltage devices.

Even perfect shields fail with poor aperture design. Learn how slot orientation, size, and placement affect shielding effectiveness, and discover why multiple small holes outperform single large openings using Babinet's principle.

FICDM testing wasn't designed for today's tiny chiplets and flip chip assemblies. Part 1 explores critical challenges: probes too large for microbumps, unreliable air discharge below 250V, and the mounting dilemma for bare die products.