Do Devices on PCBs Really See a Higher CDM-like ESD Risk?

Editor’s Note: The paper on which this article is based was originally presented at the 36^th Annual EOS/ESD Symposium in Tucson, AZ, and was given the award for the Symposium Outstanding Paper in 2015. It is reprinted here with permission from the ESD Association.

There are several scenarios where integrated circuits (ICs) are mounted on printed circuit boards (PCBs) which might be charged-up and experience charged-device model (CDM)-like events. Those discharges are thought to be significantly more critical for the IC than a CDM event of single devices during qualification. This article analyzes the CDM-risk for ICs on boards in terms of discharge waveforms.

Motivation

Because of the continuing trend of silicon technology scaling and more complex device architectures, single devices (integrated circuits, ICs) are getting increasingly sensitive to electrostatic discharges (ESD). While the Human Body Model (HBM) reproduces a discharge which today is rarely a threat in “real world” during processing and assembly due to the improved protection measures, Charged Device Model (CDM) events has become the ESD real world threat due to automated handling during processing and assembly. The increasing sensitivity of ICs results in a recommended CDM target specification for products of 250 V instead of the common 500 V target [1].

Certainly, there are real world scenarios which endanger ICs during processing and assembly. However, using basic CDM control methods [2][3] and ESD process assessment methodologies [4] 250 V should be a safe CDM level for manufacturing devices. However, there is an ongoing discussion that ICs are much more endangered by CDM- like discharges when mounted on Printed Circuit Boards (PCBs). These discharges are commonly called “Charged Board Events” (CBE); several case studies report on CBE events, see e.g. [5][6].

As the capacitance of a board is significantly larger than the capacitance of a single device, it is commonly said that CBE causes a much higher stress to the IC mounted on a board compared to the CDM event to a single IC. This statement which raises significant fears sounds quite obvious, however, it is based on some assumptions which might or might not be valid. Voltages occurring in a process step on a PCB can typically be measured rather easily and sometimes the occurrence of an ESD event can be confirmed by an ESD event detector – but all of these methods are indirect measurements and cannot assess the real risk which a device sees during such a CDM-like event on a board. It is particularly important to understand that the voltage measured in a process step cannot be simply related to any voltage in a CDM qualification test [7].

The only metric which definitely relates to a risk of damaging an IC is the (time-dependent) discharge current waveform. For CDM-like events, the peak current of the discharge is one of the critical parameters. However, in a process, from practical perspective it is rather difficult, sometimes even impossible, to measure the discharge currents directly. Therefore, there is also no direct correlation to any qualification level possible.

In this article, typical discharges of boards through a device pin are recorded and compared to discharges of single devices. After a hypothetical description of risk scenarios in a PCB production and the description of the discharge probe and the samples, we will discuss a typical example of a discharge of a form-factor board in a mobile assembly line. As direct charging is not the only possible charging mechanism, the influence of fields will be evaluated, too.

Possible Risk Scenarios in a PCB Production

CDM according to the device level test standard [8] is describing a scenario where the device is charged up and discharges into a rather big metal ground plane, at least bigger than the device. But do we have such a scenario in the field?

As long as the device is still not molded, there are only a few processes where a hard discharge could happen at all. One of the first critical process steps in which CDM like failures have been found is wire bonding. If the die is still charged when the grounded wire makes contact with the chip, a hard discharge will occur. But here we do not have a discharge into a big metal plate but only into a grounded wire where the discharge current is definitely different and the stress less stringent than in the tester.

Unfortunately, it was not possible to measure a discharge current in a real wire bonder. If they have a metal tip, the tip is too thick to put it through the current probe (CT-1). If an insulative tip is used the bond wire is grounded immediately after the tip at a clamp and it is also not possible to place a current probe there. But the setup of a wire bonder means also that the discharge scenario can easily be simulated by a discharge head with and without a metal plate (which acts as virtual ground).

A stress scenario comparable to the device level qualification test is handling in an automated test equipment (ATE) where the discharge waveform is similar to the tester, at least if the discharge is probed with a CDM (JEDEC) test head.

Once the devices arrived at the manufacturer there is normally only one process step, where a CDM event of the device alone can happen: the placement of the device onto the Printed Circuit Board (PCB). If the suction cup is insulative or simply not grounded, charge can be accumulated on the tip, which can induce charges on the device. Hence the device can charge up and discharge into the PCB, which might have a bigger capacitance than the device alone.

As soon as the device is on the PCB a “single device CDM event” is no longer possible. The so-called “Charged Board Events” (CBE) are said to be more critical than the device level CDM and several case studies report about this [5][6].

But here it has to be differentiated between an event where the charged PCB is contacted anywhere on the board near the pins of a device or at connectors of the PCB.

A typical process step where the PCB is contacted in the middle of the board is the pogo-pins contact the board from underneath are very often made of highly insulative material. The same applies for the plastic covers of the ICT; they all can charge up during the process and induce voltages on the device on the PCB that are discharged in an uncontrolled way during the test contact. But this contact is only made with a grounded needle while a bigger ground plane might be far away. This discharge is definitely less stringent than the one into a big ground plane as will be shown experimentally later.

But at least most of the current is flowing through the IC of interest, since the discharge contact is on the IC itself.

But how is the stress like at final testing when the contact to the PCB is no longer in the middle of the PCB but through the connectors only? Now the discharge current is limited by many other elements on the board. Measurements will show later how the discharge current looks like compared to the single device and to a scenario where the PCB is contacted near the IC.

During many process steps the PCB is also not directly charged but might be contacted in the presence of an external field. When the PCB is transported on the conveyor belt through production it will pass many process steps where insulative covers can induce a charge separation on the PCB. The paper will also discuss (supported by measurements) how critical fields from underneath or the side are for the ICs on the PCB.

Experimental Details
Measurement Techniques

For the discharge current measurements, a discharge head was designed which can be used rather flexibly (see Figure 2). Similar to a discharge head in a CDM test system, the discharge head has an exchangeable pogo pin and a 1-ohm resistor to ground. The pogo pin is fed through a Tektronix CT-1 current transducer which allows direct measurements of the discharge current through the pogo pin, although bandwidth-limited to about 1 GHz. The discharge current could also be measured by voltage probes as a voltage drop across the 1-ohm resistor at higher bandwidth (up to 20 GHz). Oscilloscopes with a bandwidth of 8–15 GHz are used to record the waveforms. To simulate different real scenarios, top ground planes with different geometry and material can be used.

In the course of the experiments, the discharge head was modified significantly. In order to reduce influence of parasitic capacitances, inductances and resistances in the discharge head as much as possible and record the “true” waveform, the design of the discharge head was shrunk considerably (see Figure 3). The home-made discharge probe was used to discharge PCBs, but also single devices. With its size and flexibility, the modified discharge head was successfully used for ESD process risk assessment in a production line. The recorded waveforms for CDM on single devices are compared with a commercial CDM test system Thermo Orion-2.

Before all discharges, the charging of the devices are measured by a static voltmeter Trek 347 and/or directly at the discharge pin by contact-voltmeters Trek 821 HH and Prostat CVM 780.

Samples

For the study several different modules, PCBs and single devices are used. The modules and PCBs cover a wide variety of different applications, e.g., mobile communications, automotive, industrial.

The data discussed here are taken mainly on a form-factor board used for functional verification of a mobile system and the corresponding baseband IC used in this system, see Figure 4. At one of the form-factor boards, the base band IC is not placed which allows the separation of the contribution of the board and the base band IC to the discharge.

Further experiments presented in this study are performed on chip-cards.

Results
Comparison of Discharge Heads

In a first step, the feasibility of the home-made discharge probe was proven by comparison with a commercial CDM test system. Discharge currents have been taken on a baseband IC, charged in a CDM system to 250 V, 500 V, and 750 V. The discharge current waveforms at nominal 500 V (equivalent to roughly 600 V “real” pre-charge voltage) are shown in Figure 5. From the numerical analysis of the CDM discharge waveforms, the parameters like e.g. capacitance of the device-under-test C0, equivalent discharge resistance Req, and equivalent inductance Leq are deduced by use of an RLC model as introduced by Maloney and Jack [9] and a simple SPICE circuit simulation of an RLC equivalent circuit.

Over the entire voltage range, the peak currents measured with the CT-1 in the home-made discharge probe are 15–20 per cent smaller compared to the peak currents of the discharges recorded by the CDM qualification tester.

Calculating the current from the voltage drop across the 1-ohm resistor in the discharge probe results in higher values for the discharge currents, for the version v2 of the discharge head close to the discharge currents measured in the CDM system. However, the difference between the peak currents obtained by a CT-1 and the 20-GHz voltage probes are only about 10 per cent, far less than expected due to the significant bandwidth advantage of the voltage probe; see Figure 6. As reflections occur due to the not optimized shielding in the home-made discharge head which complicate the analysis of the discharge waveforms significantly, the CT-1 measurement became the “standard” method in our study. The CDM parameters are pretty much in the same range for both type of measurements. For the baseband IC, a capacitance in the CDM tester of (11 ± 1) pF was deduced; Req was roughly 25 Ω and Leq approximately 20 nH for both measurements.

It was already discussed in [7] that the situation in a CDM qualification test system according to ANSI/ESDA or JEDEC might be a worst-case scenario. To confirm this assumption, the IC was placed on an IEC table (which is basically a big grounded metal plate covered by a thin insulating foil, see [10]), charged to 500 V and then discharged with the home-made discharge probe. Although the experimental set-up seems to be quite similar to the set- up in a CDM qualification test system, the peak currents and the derived capacitances are typically at least 25 per cent lower compared to the qualification tester (Figure 7).

This is again a good indication that the CDM thresholds obtained in a CDM qualification test are worst case for handling issues of single devices and in real world events the corresponding charging which leads to a fail needs to be significantly higher.

Charged Board Event versus Charged Device Model

As expected, the discharge waveform changes considerably when the baseband IC is mounted on a PCB which is lying on an IEC table (see Figure 8) – again, a kind of worst-case scenario with respect to capacitance. In addition to the first peak which has a very similar shape compared to the CDM discharge of the baseband, there are further contributions in the discharge waveform on a longer time range.

From the shape of the waveform with the three distinct peaks one could conclude that the discharge of this particular boards consists of three components. Assuming that the equivalent CDM resistance Req and the equivalent inductance of the discharge Leq is determined mainly by the discharge head and the arc, the values should be similar for discharges of single ICs and the PCB.

Over a charging voltage range from 250 V to 750 V, the charge stored prior to the discharge increases linearly and the total capacitance calculated from the total charge is almost constant at 80 pF which is about one order of magnitude larger than the capacitance of the baseband IC itself lying on the IEC table (11 pF), see Figure 9. In the first peak, a charge is stored which is equivalent to a capacitance of approx. 30 pF. With this simple mathematical analysis of the waveform, the discharge of the PCB allows a deconvolution into the discharges of three capacitances with 30 pF (first peak), 10 pF (second peak), and 40 pF (third peak), de-coupled by 50-ohm resistances and inductances of 100–250 nF.

Again, the differences between the waveforms taken by a current transducer CT-1 and by voltage probes are rather small (see Figure 10). Both measurements give almost identical peak currents, rise times, and full-width half maxima. Thus, it is not surprising that the total charge and the charge in the first peak is identical.

However, the peak current of the discharge of the board through the baseband pin is only 20–30 per cent higher than the peak current of the CDM discharge of the baseband IC. If the primary failure mechanism would be caused by the peak current only, we could expect that the discharge of the board gives similar failure thresholds. But with this assumption we could not explain CDM-like failures from boards/systems that have been reported to happen at voltage levels where the single device still survived. Obviously, the contributions to the waveform after the initial peak play a significant role. This part of the waveform depends mainly on the PCB and the discharge location. Typically, the maximum current of the second part of the waveform is between 10–50 per cent of the initial peak current and its duration is 10–50 ns, therefore, coming into a typical “energetic” HBM regime with rather high energies compared to a HBM target level and a different discharge scenario (one-pin discharge instead of two-pin model).

Discharge Scenarios

In fact, the situation of a board or system lying directly on the ground reference plane of an IEC table (separated only by a 0.5 mm thick isolating layer) itself is already a worst-case scenario and not very likely to happen in real world processes. In assembly lines or in the field, the distance to ground is typically much larger, and, hence, the capacitance is much smaller. But this results in lower discharge currents in reality then in a CDM-tester. This can very easily be shown with smart cards. Modern banking cards have not only a contact-based chip implemented in the card but the chip is also connected to an antenna (for contactless operation). During ESD testing such a card lies directly on a metal surface, but in reality (like in the field or during manufacturing) ground might be further away. This was simulated by placing the card on a glass surface which rests on two wooden bars (see Figure 11).

The respective discharge currents are shown in Figure 12. In both cases the smartcard was charged to 500 V, but since ground was further away for the card on the glass, the discharge current was much smaller and therefore the stress for the card was lower as well.

The same would apply for a PCB running on a conveyor system supported only at the side (open back). With a PCB placed isolated on top of the same two wooden bars with ground about 5 cm away, the discharge current was reduced dramatically.

Another scenario that easily could be simulated with the smartcards is the fact that in a CDM-tester the discharge current has a big grounded metal plate acting as virtual ground for the discharge at a distance of less than 1 cm. In reality this is normally not the case; e.g. in an In-Circuit tester (ICT) the pogo pins for testing are pretty long with ground being a couple of cm away. Figure 13 shows the difference in the discharge current if the virtual ground plane is further away or missing more or less completely. As can easily be seen, the further the ground where the discharge goes to is away (i.e. the smaller the capacitance is whereto the discharge goes) the smaller is the discharge current. Again, the CDM tester is more stringent than reality.

The same of course applies for a PCB as can be seen in Figure 14 where the discharge currents of a PCB measured with the virtual ground at a short distance (normal pogo pin) and at a long distance (long pogo pin). Also here, the discharge current with the longer pogo (i.e. the smaller capacitance to be discharged to) is significantly smaller than with the short pogo pin (what is closer to the CDM tester). If the discharge goes even to a material with a higher resistance (in this case 10 kΩ), the peak current is reduced dramatically.

Not only has the position of the board with respect to ground planes influenced the discharge waveform, but also the charging method. A charged plane in close distance parallel to the board (or the device), with a field perpendicular to the board, will have almost the same charging effect as a direct charging, similar to the situation in a CDM test system. However, an electric field parallel to the board plane has a much weaker effect. To prove this, a typical scenario from the field was simulated by placing the PCB isolated on two wooden bars with open back in front of a vertical metal plate, as can be seen in Figure 15.

Although the PCB had only a distance of approximately 2 cm to the vertical metal plate charged to 500 V, the board could not charge to values above 150 V which results in a factor of three lower stresses to the peak currents. Dielectric materials between the source of the electric fields and the board reduce the charging of the board further.

Only at a voltage of approximately 3,000 V on the vertical metal plate, a voltage of approximately 500 V could be measured on the PCB. The resulting discharge current (Figure 16) was even less critical compared to the directly charged PCB. Again the typical scenario in reality is less stringent than what the device/PCB would see in a CDM tester.

Summary and Conclusions

This article indicates that there are nearly no process steps in a PCB production line where a “single device CDM event” can happen but more possibilities for a “Charged Board Event.” Discharge current measurements taken on single devices and PCBs show that the peak current from a board discharge is not significantly higher than that from the same single device at a comparable voltage level. But of course the total amount of charge transferred through a device pin is significantly higher, resulting in a comparably long (10–50 ns) but lower discharge current waveform following the initial peak. This seems to be a higher stress to the devices since many case studies have been reported where devices are irreversibly damaged on a board at a voltage level that the single device would have survived during CDM qualification.

It was also shown that the stress in the field is typically more relaxed since in production ground is typically further away than in our tests, resulting in a lower capacitance of the board and in a lower discharge current. The stress for the devices on the PCB is also lower if the PCB sees only a parallel field rather than a perpendicular field what is the case with most of the covers in production machines.

References

1. Industry Council on ESD Target Levels, White Paper 2: “A Case for Lowering Component Level CDM ESD Specifications and Requirements. Revision 2.0,” Apr. 2010.
2. ANSI/ESD S20.20-2007: “Protection of Electrical and Electronic Parts, Assemblies and Equipment,” March 2007.
3. IEC 61340-5-1: “Protection of Electronic Devices from Electrostatic Phenomena – General Requirements,” August 2008.
4. ANSI/ESDA TR17-01-04, ESD Process Assessment Methodologies in Electronic Production Lines – Best Practices Used in Industry; to be published 01/2014.
5. A. Olney, B. Gifford, J. Guravage, A. Righter, “Real- World Charged Board Model (CBM) Failures,” Proc. EOS/ESD Symp. 2003, 34–43.
6. J. Paasi, H. Salmela, P. Tamminen, J. Smallwood, “ESD sensitivity of devices on a charged printed wiring board,” Proc. EOS/ESD Symp. 2003, 143–150.
7. R. Gaertner, W. Stadler, “Is There Correlation Between ESD Qualification Values and the Voltages Measured in the Field?” Proc. EOS/ESD Symposium 2012, 198-207.
8. JEDEC JESD22-C101C: “Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components,” 2009.
9. T. Maloney, N. Jack, “CDM Tester Properties as Deduced from Waveforms,” Proc. EOS/ESD Symposium 2013, 380.
10. IEC 61000-4-2:2009 (revises IEC61000-4-2:1995): “Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test,” 2009.

Reinhold Gaertner received his diploma in physics from the Technical University of Munich in 1987. Then he joined the Federal Armed Forces University Munich, where he was working on measurement techniques for ESD protective packaging materials. After working as an independent ESD consultant, he joined Siemens Semiconductors in 1996; which is now Infineon Technologies. He is responsible for all problems regarding external ESD protection at Infineon worldwide and also for problems in customer production, as well as for ESD device testing for qualification. Since 1989, he has lectured on static control and since 1991, he has been an active member of the German ESD Association, where he has been acting as vice president for the last couple of years. Since 1995, he has worked in the ESD standardization of IEC TC101, where he is currently convener of two working groups (static decay and device testing). In 2009, he received the outstanding contribution award of the ESDA and in 2011 he joined the ESDA board of directors.

Wolfgang Stadler received his diploma degree in physics in 1991 and in 1995 the PhD degree from the Physics Department of the Technical University Munich. 1995 he joined the semiconductor division of Siemens, which became Infineon Technologies. His focus was on development of ESD-protection concepts in CMOS technologies and on innovative ESD topics. Since 2003 he was responsible for the experimental characterization of I/O cells. He was coordinator of several European and German ESD funding projects. In 2011 he joined Intel Mobile Communications (IMC). At IMC he is now responsible for ESD/latch-up testing and qualification, for ESD control programs, and ESD fab support. Additionally, he is teaching Electronics at the University of Applied Science in Munich. Wolfgang holds several patents in ESD-related topics. He is author or co-author of more than 100 technical papers and has co-authored a book on ESD simulation. He received several Best Paper Awards and gives regularly courses on ESD device testing, ESD qualification, and ESD control measures. He is an active member of the German ESD Association and the ESDA working groups related to device and system level testing and process assessment. Since 2011, he has been the committee chair of the ESDA Working Group 5.4 on Transient Latch-up and since 2013 he is co-chairing ESDA Working Group 17 on Process Assessment. He was elected to the Board of Directors to serve the ESD Association for 2014–2016.