Bruce Archambeault

It is well known (but often forgotten) that the concept of inductance, without defining a complete loop of current, is completely meaningless! Some books give inductance of a length or wire, some people talk about the inductance of a via, and still others talk about the inductance of ground braids, etc. All these discussions about inductance ignore the requirement for a complete loop before the total or loop inductance can be discussed in any meaningful way.

This is a true story. When I first joined IBM as an EMC engineer, my new manager handed me a document titled ‘EMC Design Process at IBM’ and asked me to comment. I quickly read the short document that basically said that the EMC engineer would provide the design engineers a list of EMC rules, which would be largely ignored.

This article investigates the impact of ground vias placed in close proximity to high speed differential signal vias and the resulting differential mode to common mode conversion. The work shows the influence of the distance between ground (GND) vias and differential signal (Diff. SIG.); the effect of the asymmetrical configuration of the GND vias; the impact of the dielectric thickness and the number of transitions between the planes.

This paper describes how to remove the measurement artifacts caused by discontinuities in high frequency S-parameter data caused by the test connectors on the Printed Circuit Boards (PCBs) and cables. The frequency domain S-parameters are converted to the time domain to get the impulse response. Time domain gating is then used on this impulse response to remove reflections due to end connectors and/or other discontinuities. The gated impulse response is then transformed back to the frequency domain. The final result is a much improved S-parameter data set with unwanted resonance removed, allowing the PCB trace or cable loss to be determined.