Hot Topics in ESD

This is the second of a two-part series on transmission line pulse (TLP) testing.

Author’s Note: This is the first of a two-part series on the TLP Zoo,...

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

If you really want to know whether your footwear and flooring are working together, measure the resistance from the wearer via footwear and flooring to earth (ground).

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere.

Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.

The 2020 EOS/ESD Symposium featured a new EMC Special Session, organized in cooperation between the EMC Society and EOS/ESD Association. This Special Session was planned to emphasize the relationship between EMI/EMC and ESD.

The EOS/ESD Association is addressing the various vectors of development needed to support 3D packaging ESD integration and manufacturing ESD control.