Columns

Is it safe to use cellphones on airplanes? The real question should be: “Is it safe for passengers to use any electronic equipment on airplanes?”

We continue to focus on the AC/DC power converter board (2-layer PCB). We evaluate the implementation of several EMC countermeasures and present the conducted and radiated emissions results performed according to the CFR Title 47, Part 15, Subpart B, Class B.

Author’s Note: This is the first of a two-part series on the TLP Zoo,...

This is the eighth article in a series of articles devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters and employ different ground techniques [1-7].

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

History is very telling in influencing the trajectories of product safety and liability. To get the details, we turned to insight from Doug Nix, Managing Director of Compliance inSight Consulting and lead author of the Machinery Safety 101 blog. Read the interview with Nix for context on how the past has shaped the ideology and approaches that we employ today.

Operating my personal document shredder crashes my digital TV set-top box, although it is 5 metres away. Toggling the on/off button on the set-top box restores normal operation. 

This is the seventh column in a series devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters, and employ different ground techniques .

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

This article focuses on PCB layout considerations and the design of the reference return paths for the one- and two-layer boards.