A 1kV Discharge Directly onto a Staple Leads to Increased Energy Penetration Inside Metallized Static Shielding Bags

Editor’s Note: Due to the overwhelming amount of positive feedback from the September 2013 issue of In Compliance Magazine (pp. 42-48), a follow-up article with additional lab testing by the author was necessary to respond to an aerospace prime.

Thank you for your informative article on “Pin Holes & Staples Lead to Diminished Performance in Metallized Static Shielding Bags.” Have you considered what happens if there is an ESD discharge to the staple in a bag?

Outstanding question! If the reader will recall from last month’s article, initial lab testing was conducted by the author for Type III static shielding bags to ANSI/ESD STM11.31-2012. According to the ESD Association, “This standard test method provides a method for testing and determining the shielding capabilities of electrostatic shielding bags.”

Figure 1

The reader may remember from last month’s article that ESD shielding bag excessive wear, stapling and pin holes can pose device protection risks. The size and magnitude of the pin holes influences bag attenuation from a high voltage discharge (HVD). In the previous study, stapled Type III static shielding bags were subjected to 1kV discharges in close proximity to staple(s) or pin holes. As a reference point, the calibrated discharge (metal to metal) generated 49,794.96 nJ. The first test consisted of a new static shielding bag (free of staples) that was subjected to six 1kV discharges; the average energy penetration was 17.95 nJ (Figure 2 right). According to Mil-PRF-81705E, passing equals 10nJ Max, ANSI/ESD S11.4, passing equals <20 nJ and for ANSI/ESD S541-2008, passing equals <50 nJ. Therefore, the bag passed S11.4 & S541.

Figure 2

Subsequently, the author subjected a stapled bag to ANSI/ESD STM11.31 testing with a staple in close proximity to the capacitive probe as illustrated in Figure 3.

Figure 3

Figure 4

Therefore, an average discharge energy (nanojoules) seen inside the bag from the offset staple in close proximity to the capacitive probe at 1kV discharge measured was 21.23 nJ.

In this brief overview, another stapled bag was positioned under the ANSI/ESD STM11.31 capacitive probe fixture, slightly offset, before undergoing a 1kV discharge (Figure 5). A whopping 876.38 nJ penetrated the bag when a metal capacitive probe discharged onto the metal staple.

Figure 5

Figure 6

Consequently, final testing took place when the capacitive probe was firmly clamped into place and directly centered over the staple as illustrated in Figure 7. And, as Figure 8 illustrates, an impressive 1078.27 nJ penetrated the bag!

Figure 7

Figure 8

From Table 1, the reader can review the entire data tested at 12%RH, 73.40F after 48 hours of preconditioning.

Table 1

Table 2

In short, one could conclude that stapling a bag is an egregious act for ESD control. The author welcomed the defense contractor’s inquiry which in turn prompted additional analysis. One may not be able to prevent pin holes or puncturing of a static shielding bag, but the unconventional act of stapling bags can be reined in so as not to compromise the integrity of an ESD control program. The reader can review the previous article on the risks of pinholes and staples by clicking here.

REFERENCES

• ANSI/ESD S541, ESD Packaging & Materials Standard
• ANSI/ESD S11.4 (Static Shielding Bag Standard)
• Following ESD Materials Validation Process, Controlled Environments, Bob Vermillion, August 26, 2010
• A US Army DAC Study, March 2012, Vermillion and White
• ESD from A to Z, Second Edition, Kolyer & Watson, Chapman & Hall, 1996
• Humidity & Temperature Effects on Surface Resistivity, John Kolyer and Ronald Rushworth, Evaluation Engineering, October 1990, pp. 106-110
• Packaging’s Fight Against ESD (RFID), Medical Device-network.com, March 2010, Doug Smith and Bob Vermillion
• Pin Holes & Staples Lead to Diminished Performance in Metallized Static Shielding Bags, In Compliance, September 2013, pp 42-48, Bob Vermillion

BOB VERMILLION, CPP/FELLOW Certified ESD & Product Safety Engineer-iNARTE is a subject matter expert in ESD mitigation of materials and packaging and is an ESDA Standards Committee Member. In 2010, Bob was the first to present on suspect counterfeit ESD packaging in the supply chain at the NASA-QLF. RMV is located on-site at NASA-Ames Research Center and is a NASA Industry Partner. Bob publishes numerous articles and white papers on advanced materials, packaging non-compliance and suspect counterfeiting in manufacturing, materials handling, shipping and long-term storage for the aerospace/defense, medical and electronics sectors. Speaking engagements include invitations from the DOD, DOE and NASA to present on supplier Iisues with materials and packaging. RMV is a NASA approved ESD laboratory at NASA-Ames. An internationally recognized author and inventor, Bob develops professional level ESD packaging seminars for Cal Poly, SJSU, UC Berkeley, Loyola Marymount, Clemson University and Oxford University. RMV is a 3rd Party ESD material testing, training and consulting company. Bob Vermillion is an active member of SAE G-19 Counterfeit Components and SAE G-21Counterfeit Materiel Committees. Bob can be reached at 650-964-4792 or email Bob at bob@esdrmv.com.