Wei Liang

Wei Liang leads ESD and Latchup strategies for Intel AMS IPs. Previously, he worked on the GlobalFoundries ESD team. Wei holds an MBA from Boston University and a Ph.D. in Electrical Engineering from UCF. He has authored more than 20 peer-reviewed papers and holds more than 10 U.S. patents in ESD.

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Machine Learning Applications in the Novel ESD Compact Modeling Methodology

This column explores the application of machine learning techniques in ESD compact modeling for semiconductor devices. It compares traditional methods with a new machine learning approach, highlighting improved efficiency and accuracy in predicting ESD protection performance.

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What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.

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Wei Liang

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