A new version of Technical Report TR18.0-01-25 (TR18) on ESD Electronic Design Automation (EDA) Checks by the ESD Association’s Working Group 18 is about to be released. This article provides an overview of TR18, which offers guidelines for the EDA industry and the ESD design community to establish a comprehensive ESD verification flow. This flow addresses ESD design challenges in modern ICs, including common terminology and required check types. The main requirements are broad check coverage, manual checking limitations, transparency, and integration into the design flow for clear and actionable violation reporting. The document covers generic checks, EDA toolsets, and databases, allowing IC design companies, IDMs, or foundries to implement specific rules in their design and verification flows for automated checking.
ESD Checks Throughout the IC Design Flow
ESD checks for an IC product design are performed at multiple phases throughout the product design. These checks need to be coordinated with the ESD development and implementation flow, supported by an ESD check flow. The main phases of the product design flow are:
- Technology Enablement Phase
- Product Definition Phase
- Product Architecture Phase
- Product Design Phase
- Product Verification Sign-off Phase
- Product Validation Phase
The main ESD checks include:
- Schematic-based Topological ESD Checks
- Layout-based ESD Checks
- Package-level ESD Checks
- System-level ESD Checks
- ESD Circuit Simulation (SPICE)
- ESD TCAD Simulation
The timing of EDA check execution throughout the design flow is indicated with grey shapes in Figure 1. Most ESD checks must be run during all design phases, with accuracy depending on design data maturity and completeness. Standardization of input and output data and interfaces is crucial for ESD EDA verification. The ESD engineer should consider the complexity and size of the checked database to build an efficient ESD verification flow.
Schematic-based Static Topological ESD Checks
Static topological checks include verifications implemented with commercial or customized EDA tools capable of analyzing netlist topologies. These checks verify devices that need ESD protection and ESD protection networks (Figure 2a and 2b). They consider schematics information and the electrical behavior of the circuit. Topological checks are typically run on netlists derived from schematic views but can also be run on layout-extracted netlists, including RLC parasitics for analysis.
ESD integration rules can be derived from SPICE and TCAD simulations or (VF-)TLP measurements to match required ESD industry standard levels. Topological checks ensure IC design compliance with predefined integration parameters and appropriately sized circuit structures for desired protection. These checks need additional ESD-specific input information for analysis. They are especially useful at early design stages when databases are partial and schematic views are available while layout information is limited. Topological checks accompany all IC product design flow phases with suitable verifications, depending on available data and completeness.
Layout-based ESD Checks
ESD verification must also include layout-based checking to verify the construction of ESD protection devices, identify weak ESD paths due to the creation of unintended parasitic devices, and perform a detailed analysis of back-end metallization. Layout-based ESD checks include broad classes of checks (Figure 3a and 3b):
- Geometrical Design Rule Checks (DRC)
- Logic Driven Layout (LDL) checks
- Current Density (CD) checks
- Metal routing Point to Point (P2P) resistance
The design database should include geometric information of the target circuit under check (e.g., layout or floorplan) and annotation of relevant metallization (e.g., IO/power/ground net type, voltage level, etc.). The tool flow may involve one or more commercial EDA vendor solutions plus additional means developed in-house for customized ESD robustness analysis. ESD devices are at the core of the ESD protection schemes and are the most critical elements in the discharge paths. They are often characterized by TLP/VFTLP measurements. Verification rule files (often from a foundry) are used to describe the relevant portion of the system to analyze and the constraints to be checked. The final output is used to visualize and confirm whether the design violates the design constraints.
Conclusion
In this first part of the article, the concept of ESD checks throughout the IC design flow was covered, together with schematic-based and layout-based ESD checks sections.
In Part 2, package‑level and system-level checks sections, together with ESD circuit simulation and ESD TCAD simulation sections, will be handled, completing the coverage of all ESD EDA checks described in the Technical Report.
