Resistance

Are you just getting into software simulation and feeling a little overwhelmed with all the new jargon? This brief article will explain some of the most common terms used in the very exciting world of EMC/Signal Integrity simulation software, all in one location.

Confusion over ESD flooring resistance terminology and requirements abounds, leaving many in the dark and creating potential risks. This article helps to clarify this complicated issue so that you can work to mitigate the problem.

CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.

In the past six months, EOS/ESD Association, Inc. released eight new or revised documents on electrical overstress (EOS), grounding, packaging materials, seating (chairs), footwear, hand tools, gloves, and human metal model.

Robust ESD protection does not ensure that IC designs are protected from unintended EOS effects. This article identifies areas of risk in some ESD design methods.