Why Tunnel FETs?

Past, Present and Future of Tunnel Field Effect Transistors: Part I

The answer to this question is linked with breakdown of Moore’s law and Dennard’s scaling theory. In the last two decades, MOS technology has seen a significant progress in terms of scaling down from sub-micron feature sizes to sub-10nm dimensions. To give a quantitative feel, the gate length, gate dielectric thickness and junction depth have been reduced by about three orders of magnitude in the past 20 years, which has significantly improved the power-performance metrics. However, in recent times, the scaling pace has slowed down (for example, a 11nm technology node doesn’t have 11nm gate length devices anymore). The minimum gate lengths are still around 20 – 24nm. This is attributed to an increased S/D leakage, weak gate control and higher power consumption at very short gate lengths. To address this, power supply (V_DD) scaling is desired; however, to meet the ON current requirements, i.e. performance targets, the threshold voltage needs to be scaled along with VDD. However, leakage current increases exponentially as threshold voltage is reduced. Hence, threshold voltage has become a non-scalable parameter, as any decrease of threshold voltage exponentially increases the leakage current, which is mainly because of MOSFET’s fundamental limit of subthreshold swing (60mV/dec at room temperature). In reality, owing to the short channel effects, subthreshold swing (SS) is far worse than the ideal value of 60mV/decade.

Around the same time when Dennard’s scaling theory practically became difficult to implement (late 90’s), a significant increase in requirement for low power technologies for wireless and handheld applications was seen. The surge in handheld consumer electronic devices like smart phones, smart watches and tablet PCs requires minimization of active as well as static power dissipation by scaling down the supply voltage below 0.5V, while maintaining acceptable performance targets. It was therefore well accepted that in order to reduce the leakage current and scale supply voltage, it is important to explore new device structures, which can offer sub-threshold swing values below 60mV/decade. MOSFET devices, which work on the principle of thermionic injection of carriers from source to channel, do not offer enough design space and therefore limit the supply voltage scaling. To account for the future roadmap, several CMOS-like devices such as the Nanowire Gate All Around (GAA) MOSFETs, FinFETs, carbon nanotube field effect transistor (CNTFET), Impact ionization FETs (I-MOSFET), and TFETs were demonstrated by various groups, in order to minimize the short channel effects (SCE) and to lower the source-drain leakage current. Among these devices, only TFET and I-MOSFET promise a SS less than 60mV/dec and improved short channel performance, which is attributed to fundamentally a different mechanism used for carrier injection from source to channel. However, given the fact that I-MOSFET requires very high voltage operation, TFET is the only promising solution available beyond FinFET and Nanowire FETs. Tunnel FET fundamentally offers a very steep sub-threshold slope, thereby allowing threshold voltage and VDD scaling beyond CMOS limits without affecting the static leakage and ON currents.

Quick Review

In the last 15 years there have been extensive investigations on Tunnel FET devices for ultra-low power and high-performance operation. Tunnelling phenomena allows sub-60mV sub-threshold operation thereby has a potential to scale leakage and improve ON current at lower supply voltages. The very early TFET concept of gated P-i-N diode configuration, despite several advancements like SiGe source, Low-k drain spacer, high-k source spacer, low drain doping, highly doped source, abrupt source junction profiles, post silicidation implant, band gap engineering and double gate architectures, suffered from extremely low ON currents. This was primarily attributed to limited tunnelling cross-section/area available in gated P-i-N diodes (also known as point tunnelling FETs) [1]–[9]. To overcome this problem, vertical tunnelling [10], [11] / area scaled tunnelling [12], [13] / line tunnelling [14]–[16] devices were proposed, which theoretically show significantly improved ON current, reduced leakage and subthreshold swing which can be attributed to an increased tunnelling cross section and gate-field aligned binary tunnelling mechanism [17], [18]. However, there are still open concerns related to TFET design in terms of dealing with trap assisted tunnelling (TAT) [19] and diffused junction profiles [20], which adversely affect the ON current and cause an increased leakage and SS of area scaled tunnelling or vertical tunnelling devices.

Circuit Advantages

As mentioned above, higher SS limits the supply voltage scaling, which further increases the power dissipation (∝ I_OFF V ³_DD). Higher power dissipation at shorter channel lengths necessitates supply reduction, which however is limited by higher SS. To reduce the SS and thereby allow supply voltage scaling, one requires relying on carrier injection methods other than thermionic injection. A sub-thermionic injection device is expected to offer better energy performance compared to MOSFETs, as depicted in Figure 1 [21].

Figure 2 compares the input characteristics of some of the potential candidates for sub-thermionic operation. These are NEMS switches (Nanoelectromechanical systems) ([22], Negative capacitance FET (NCFET), Impact Ionization FET (I-MOSFET) [23] and Tunnel FET. NCFETs and I-MOSFET require a certain minimum voltage for their adequate operation and thereby do not allow supply voltage scaling beyond a certain point. Tunnel FET, so far, is the most promising alternative for supply voltage reduction while maintaining steep sub-threshold slope. It has potential to offer low static leakage and adequate ON current even at lower supply voltages, which minimises power dissipation without sacrificing the performance. It also combats various short channel effects such as DIBL, hot carrier effects [24] even at shorter channel lengths, which makes it a potential candidate for future technology nodes.

The subject of this month’s column will be continued in the June issue’s Hot Topics in ESD, Why Tunnel FETs? Past, Present and Future of Tunnel Field Effect Transistors: Part II.

References

1. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60mV/dec subthreshold slope,” Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2008, pp. 1–3.
2. G. Dewey et al., “Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing,” Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2011, pp. 33.6.1–33.6.4.
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4. Q. T. Zhao et al., “Tunneling field-effect transistor with a strained Si channel and a Si_0.5Ge0.5 source,” Solid-State Electronics, Vol. 74, pp. 97–101, Aug. 2012.
5. S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect transistors with record high ION/IOFF,” VLSI Technology Symposium, June 2009, pp. 178–179.
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   pp. 1671–1677, Dec. 2008.
10. K. Ganapathi, Y. Yoon, and S. Salahuddin, “Analysis of InAs vertical and lateral band-to-band tunneling transistors: Leveraging vertical tunneling for improved performance,” Appl. Phys. Letters, Vol. 97, No. 3, p. 033504, 2010.
11. L. Lattanzio, N. Dagtekin, L. De Michielis, and A. M. Ionescu,“On the static and dynamic behavior of the germanium electron-hole bilayer tunnel FET,” IEEE Trans. Electron Devices, Vol. 59, No. 11,
    pp. 2932–2938, Nov. 2012.
12. A. Rajoriya, M. Shrivastava, H. Gossner, T. Schulz, and V. R. Rao, “Sub 0.5 V operation of performance driven mobile systems based on area scaled tunnel FET devices,” IEEE Trans. Electron Devices, Vol. 60, No. 8, pp. 2626–2633, Aug. 2013.
13. R. Asra, M. Shrivastava, K. V. R. M. Murali, R. K. Pandey, H. Gossner, and V. Ramgopal Rao, “A tunnel FET for VDD scaling below 0.6 V with a CMOS-comparable performance,” IEEE Trans. Electron Devices, Vol. 58, No. 7, pp. 1855–1863, Jul. 2011.
14. A. M. Walke et al., “Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET,” IEEE Trans. Electron Devices, Vol. 61, No. 3, pp. 707–715, Mar. 2014.
15. I. A. Fischer et al., “Silicon tunneling field-effect transistors with tunneling in line with the gate field,” IEEE Electron Device Letters, Vol. 34, No. 2, pp. 154–156, Feb. 2013.
16. K.-H. Kao et al., “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets,” IEEE Trans. Electron Devices, Vol. 59, No. 8, pp. 2070–2077, Aug. 2012.
17. C. Hu et al., “Prospect of tunneling green transistor for 0.1V CMOS,” inProc. IEEE Int. Electron Devices Meeting, Dec. 2010, pp. 16.1.1–16.1.4.
18. R. Asra, K. V. Murali, and V. R. Rao, “A binary tunnel field effect transistor with a steep sub-threshold swing and increased on current,”Jpn. J. Appl. Phys., Vol. 49, No. 12R, p. 120203, 2010.
19. X. Y. Huang et al., “Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors,” IEEE ElectronDevice Letters, Vol. 31, No. 8, pp. 779–781, Aug. 2010.
20. A. Vandooren, D. Leonelli, R. Rooyackers, K. Arstila, G. Groeseneken,and C. Huyghebaert, “Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs,” Solid-State Electron., Vol. 72, pp. 82–87, Jun. 2012.
21. A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, Vol. 479, No. 7373, pp. 329–337, Nov. 2011.
22. Kam, Hei, Donovan T. Lee, Roger T. Howe, and Tsu-Jae King, “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics,” In Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp. 463-466. IEEE, 2005.
23. Gopalakrishnan, Kailash, Peter B. Griffin, and James D. Plummer, “I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q,” In Electron Devices Meeting, 2002. IEDM’02. International, pp. 289-292. IEEE, 2002.
24. A. C. Seabaugh and Q. Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE, Vol. 98, No. 12, pp. 2095-2110, Dec. 2010.

Prof. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. He is the recipient of two major international recognitions namely MIT TR35 award (2010) and IEEE EDS Early Career Award (2015). Beside these, he has received several national awards and honours namely 2018 Indian National Academy of Science (INSA) Medal for young scientists, 2017 Indian National Academy of Engineering (INAE) Young Engineer Award, 2018 INAE Innovator Entrepreneur Award, 2018 Indian Academy of Sciences (IASc) Young Associate award, 2018 National Academy of Sciences (NASI) Young scientist award, Excellence in PhD thesis award from IIT Bombay for his PhD research work in 2010 and 2008 IIT Bombay Industrial Impact Award. He has served in the TPC of more than 10 international conferences including IEDM, IRPS, EOSESD, etc.  Prof. Shrivastava’s current research deals with experimentation, design and modelling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices, high voltage devices in advanced CMOS nodes and ESD reliability in advanced and beyond CMOS technologies. He had held positions in Infineon Technologies, Munich, Germany; Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany. He joined Indian Institute of Science as a faculty member in year 2013. Prof. Shrivastava has over 100 international publications and more than 40 patents. More details related to his group or work can be found at: http://mayank.dese.iisc.ac.in.