What Are the Advantages of Capacitively Coupled TLP (CC-TLP)?

Charged Device Model (CDM) discharge events are the major root cause for Electrostatic Discharge (ESD) failures in a modern, automated production and test environment. The CDM stress testing is well established for product qualification. It simulates the possible charging of a packaged device during automated handling followed by the discharge stress event which is caused by contacting one pin with e.g. the grounded test equipment. However, due to the nature of the occurring air discharge, the CDM test shows a low reproducibility with respect to the resulting discharge pulse. The related standard [1] considers this fact by allowing a peak current variation of more ± 20 % during the tester verification process on special verification modules for pre-charge voltages below 250V. The test of real devices can show even a higher variation depending on the package and pin type. This lack of discharge repeatability can result in an expensive re-design if the device under test (DUT) does not meet the required CDM failure threshold. Thus, there is a demand for an improved repeatability stress method. 

CC-TLP – A Reproducible CDM-like Stress Method

The Capacitively Coupled Transmission Line Pulsing (CC-TLP) [2] [3] allows a much more reproducible CDM-like stress test. It uses a TLP pulse generator which produces a rectangular stress pulse and which is a well-known tool for the characterization of protection elements and circuits in the ESD domain. Unlike TLP for which both pins (signal and ground) are connected to the DUT establishing a well-defined stress path, CC-TLP connects only the signal pin directly to the DUT while the ground return path shows a capacitive connection (Figure 1).

Thus, like for the CDM, the stress pulse is injected via one pin (Pin Under Test PUT) and charges up the background capacitance Cb which represents the package capacitance with respect to the ground. This ensures the same stress current paths as in a CDM test. However, CC-TLP avoids an air discharge by contacting the PUT prior to the triggering of the stress pulse. Thus, the CC-TLP stress pulse shows a much better reproducibility which is only limited by the pulse relay contact of the applied TLP generator. Figure 2 (left) compares the variation of more than 500 CDM stress peak currents for a CDM voltage of 110 V with the CC-TLP peak currents. 

The CDM data in the 110V charge voltage area show a variation in a range of 30 % with some outliers in a range of 40%. In contrast, the variation of the CC-TLP peak currents is in a range of 5 % which demonstrates the clear superiority of this method. Figure 2 (right) compares measured CC-TLP pulses applied to a 30 pF CDM verification module with a CDM current pulse. By varying the TLP pulse width the CC-TLP pulse can be easily tailored to the required pulse width for the best match with the CDM waveform.

Figure 3 depicts a possible set-up for the CC-TLP method and a real CC-TLP probe.

The device under test (DUT) is placed on the chuck of a wafer prober. The TLP generates the pulse which passes the pick-off for the pulse voltage measurement and which is then injected into a semi-rigid 50 Ω transmission line TL. The TL ground shield connects to the ground plane and the signal line is connected to a probe needle which connects the PUT through a small hole in the ground plane. The measurement and superimposition of the incident and the reflected pulse are used to calculate the injected stress current.

With this setup, it is possible to perform tests not only at the package but also at the wafer level. This allows precise CDM relevant investigations e.g. at earlier product development stages without the need for packaging. Furthermore, the high reproducibility improves the determination of the exact failure threshold by applying smaller stress steps. This becomes relevant regarding the trend to reduce the required CDM thresholds for modern deep submicron technologies [6].

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature [3] [5] [7] [8] [9]. Figure 4 shows the comparison of a physical CDM damage signature and its replication by CC-TLP at both the package and wafer levels.

These investigations prove that the CC-TLP method is capable of reproducing CDM-related damage signatures without the disadvantages caused by the CDM air discharge. 

What is the impact on future developments?

Further investigation has also identified a sensitivity of the failure threshold on the stress pulse rise time [9] which can become relevant especially for future high-speed applications. Unlike CDM, the CC-TLP method also allows for controlling pulse rise time in a very reproducible way. Thus, it would support the designers to develop the protection for an exactly defined stress level which optimizes the trade-off between functional performance and ESD protection. Moreover, the trend to integrate several dies (each with almost no internal CDM protection) into systems in a package (SiP) or Multi-Chip Modules (MCM) also requires a test method to evaluate the single components or chips prior to the integration into the complete system or module. For these new applications, CC-TLP has also been demonstrated to be a solution. 

References

1. ANSI/ESDA/JEDEC JS-002-2018, Charged Device Model (CDM) – Device Level, EOS/ESD Association, 2018.
2. H. Wolf, H. Gieser, W.Stadler, and W. Wilkening, “Capacitively Coupled Transmission Line Pulsing CC-TLP – A Traceable and Reproducible Stress Method in the CDM-Domain,” Journal of Microelectronics Reliability, Elsevier, Volume 45, No. 2, 2005.
3. H. Gieser, H. Wolf, and F. Iberl, “Comparing Arc-free Capacitive Coupled Transmission Line Pulsing CC-TLP with Standard CDM Testing and CDM Field Failures,” Tagungsband 9, ESD-Forum Berlin 2005.
4. D. Helmut, H. Gieser and H.Wolf, “Simulation and Characterization of Setups for Charged Device Model and Capacitive Coupled Transmission Line Pulsing”, Proceedings 14. ESD-Forum Munich 2015.
5. K. Esmark, R. Gaertner, S. Seidl, F. zur Nieden, H. Wolf and H. Gieser, “Using CC-TLP to get a CDM Robustness Value,” Proceedings of the EOS/ESD Symposium 2015.
6. “Industry Council on ESD Target Levels, White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements,” Revision 2.0, April 2010.
7. H. Wolf, H. Gieser, K. Bock, A. Jahanzeb, C. Duvvury, and Y. Lin, “Capacitive Coupled TLP (CC-TLP) and the Correlation with the CDM,” Proceedings of the EOS/ESD Symposium 2009.
8. J. Weber, H. Gieser, H. Wolf, L. Maurer, K. T. Kaschani, N. Famulok, R. Moser, K. Rajagopal, M. Sellmayer, A. Sharma and H. Tamm, “Correlation study of different CDM testers and CC-TLP,” Proceedings of the EOS/ESD Symposium 2017.
9. J. Weber, R. Fung, R. Wong, H. Wolf, H. A. Gieser, and L. Maurer, “Stress current slew rate sensitivity of an ultra-highspeed interface IC,” IEEE Transactions on Device and Materials Reliability, Vol. 19, Issue 4, November 2019.