Verotec contributes to THAAD systems

The first of two Terminal High Altitude Area Defense (THAAD) interceptors is launched during a successful intercept test. The test, conducted by Missile Defense Agency (MDA), Ballistic Missile Defense System (BMDS) Operational Test Agency, Joint Functional Component Command for Integrated Missile Defense, and U.S. Pacific Command, in conjunction with U.S. Army soldiers from the Alpha Battery, 2nd Air Defense Artillery Regiment, U.S. Navy sailors aboard the guided missile destroyer USS Decatur (DDG-73), and U.S. Air Force airmen from the 613th Air and Operations Center resulted in the intercept of one medium-range ballistic missile target by THAAD, and one medium-range ballistic missile target by Aegis Ballistic Missile Defense (BMD). The test, designated Flight Test Operational-01 (FTO-01), stressed the ability of the Aegis BMD and THAAD weapon systems to function in a layered defense architecture and defeat a raid of two near-simultaneous ballistic missile targets

The first of two Terminal High Altitude Area Defense (THAAD) interceptors is launched during a successful intercept test.

Terminal High Altitude Area Defense (THAAD) is a US Army anti-ballistic missile system designed to shoot down short, medium, and intermediate ballistic missiles in their terminal phase using a hit-to-kill approach. The interceptor missile carries no warhead, but relies on the kinetic energy of the direct impact to destroy the incoming threat. Verotec has supplied Lockheed with custom 4U, 750mm deep 19 inch VPX chassis that houses a signal integrity testing subsystem, the reconfigurable and analogue Self Test Subsystem. The STS chassis validates the signal outputs from other parts of the control system to ensure their integrity.

Signals enter the STS through four high density circular connectors in the front panel. They are initially processed through FPGA-based cards, which are cooled by one of two integral high performance fan trays mounted in the base of the unit. The top and base of the chassis are fitted with high perforation covers to maximize airflow through the cards. The processed signals from the FPGA cards are propagated to a 3U 9 Slot VPX (VITA 46) system at the rear of the unit, which is housed in a heavy-duty KM6-HD card cage, powered from a 300 Watt pluggable PSU and cooled by the second dedicated fan system.  The rear panel also provides cut-outs for DIN, USB and RJ45 connectors. Signals exit the VPX section of the system to a DMM and oscilloscope, generating external data that allows the operating personnel to confirm their integrity against reference values as part of the pre-launch sequence.

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