Introduction
The last couple of months, we examined methods for simulating radiated immunity. We’ll continue our discussion with another common immunity issue, electrostatic discharge (ESD).
One reason I see ESD becoming more of an issue is threefold. Products are getting smaller with more crowded components, leading to increased coupling. Most commercial and medical products use unshielded enclosures, and finally, digital devices are now powered with lower voltages, which means the noise margin is lower.
The biggest issue for manufacturers is when the ESD test fails at certain test points. The question always arises: where is the ESD current going, and what components or systems are being affected? Typical product failures include processor reset, user interface display scrambling, or data corruption. Worse would be component destruction.
ESD is largely a high-frequency phenomenon, and the currents induced tend to travel on the “path of least impedance” described below. The challenge in troubleshooting is that the path and the components affected may not be easily assessed visually. For example, the ESD path injected into a common DRAM module can take multiple paths (Figure 1).
Human Body Model
The strong arc when you touch a doorknob creates a discharge and is modeled by a variable high-voltage and an R-C network. In the human body model, we have a parallel capacitor, C, which is charged up and discharged through a series resistor, R. The resistor can vary depending on skin resistance and other factors. Most ESD simulators use a 150 pF capacitor and 330 Ω resistor, according to the European Union’s basic ESD standard, IEC 61000-4-2.
Figure 2 shows the idealized discharge waveform according to IEC 61000-4-2. The risetime is specified as 0.7 to 1.0 ns. But when the standard was developed, the highest bandwidth oscilloscope was on the order of 1 to 1.5 GHz. The benefit of spending my career in Hewlett-Packard’s oscilloscopes division gave me the advantage in measuring ESD waveforms using scopes with bandwidths as high as 40 GHz. By the mid-2000s, I was measuring some discharges with risetimes as small as 30 ps! My belief is that the actual risetime of an ESD pulse is only limited by the bandwidth of the measuring instrument!
Measuring the ESD Pulse
An actual measured 4 kV ESD pulse using a 1.5 GHz bandwidth scope taken a couple decades ago, revealed a risetime of 575 ps (Figure 3). Accurately measuring ESD requires an “ESD target”, a roughly 2Ω load connected through 20 to 40 dB of attenuators and connected to an oscilloscope. I describe the method in an application note I wrote for Tektronix (Reference 1). Commercial EMC test labs are required to verify measurement accuracy periodically by using one of these ESD targets.
Because an ESD pulse can inject or couple large currents into your product under test, we generally need to either divert or block the ESD current using shielding, parallel capacitors or transient protectors, and series resistors or common mode chokes. Designing products to withstand ESD is a topic for another article, but there are sources that help explain the design techniques (References 2 and 3).
Figure 3 shows the waveshape of a measured 4 kV ESD pulse. This is actually a combination of two discharges as indicated in the figure. The sharp, narrow spike is the discharge of the free-space capacitance of the ESD simulator’s probe tip, and the slower, wide pulse is the discharge of the capacitor with series resistor and inductance of the simulator ground cable.
The two waveforms, a high-frequency, low-energy spike that creates a strong E-field (high voltage) and a low-frequency, high-energy wave that creates a strong H-field (high current), need to be treated differently when mitigating.
The high-frequency E-field generating pulse radiates and couples throughout your circuit if unshielded, but gets diverted around shielded products. It can generally cause soft errors, such as processor resets or data glitches.
The low-frequency, high-energy wave can generate amps of current, which must be diverted or blocked. It can cause latch-up, degradation of components, or even destroy components.
Troubleshooting ESD on the Bench
Sometimes, simply examining the product and system cables can help determine how ESD energy is coupling to your product. Simple fixes like ensuring shielded cables get properly bonded to the enclosure might be all that’s required.
Processor resets are usually solved by adding a series 1kΩ resistor in series with the processor reset pin. Sometimes shielding may be needed over known sensitive circuits.
Once the simple fixes are in place, the next challenge is determining exactly where the ESD current is flowing through your product or circuit board. Because the path ESD current takes to get back to earth depends on the “path of least inductance”, it’s difficult to know exactly what parts of the circuit are being affected. To solve this, I’ve developed an easy way to determine the path of ESD current by using an H-field probe and oscilloscope (Figure 4). For more details, I wrote this up as an application note for Tektronix (Reference 4).
This requires connecting an ESD simulator set to a low (100 to 500 volt) output so as not to destroy circuitry as you’re troubleshooting, and connecting the output probe to known points where the ESD test fails. Using an assistant or adjusting the simulator for 1-second pulses, use the H-field probe connected to the scope and scan around the system wiring or circuit board. You should be able to identify the path or paths of low impedance by watching for maximized discharges in the display.
Case Study Example
This was a perfect example where determining the actual path of ESD current helped solve the issue within a couple of hours.
I was called to assist one of my medical clients experiencing an anomaly on a new centrifuge under development. There were two particular sides on the cover that, when injected with relatively low levels of ESD, would pop open the top lid during operation. Not a good safety feature!
The lid was controlled by several solenoids, and it was obvious to the client that ESD was disrupting the solenoid circuitry. To their credit, they’d tried adding impedance to the ESD current (blocking technique) through the use of ferrite chokes on various cables, but that wasn’t helping. Because the system was comprised of a large chassis and a hinged cover, they tried bonding the two together, which also didn’t help.
Troubleshooting was complicated due to the number of cables connecting the two assemblies. After making several measurements with an oscilloscope, I thought I’d try a relatively new acquisition of a used HP 547A current tracer probe, which was the precursor technique that led me to the H-field probe and scope method (Reference 5). This probe was developed in the 1980s as a set of logic probe, current injector, and current tracer. The latter two were designed to help locate short circuits in PC boards. They can still sometimes be found on eBay or other used equipment sources.
The HP 547A current tracer consisted of a small H-field pickup loop and an incandescent light bulb in the tip (Figure 6). As the probe detected a current, the light would turn on with a level of brightness indicating the strength of the current. There’s even a sensitivity adjustment on the probe.
I had the engineer assigned to this project help by injecting low-level ESD pulses into the known sensitive spots on the system while I probed cables and boards. We soon narrowed in on the user interface and control board mounted on the front of the product. There was a high amount of ESD current induced into the cables connected to the board, and this current was flowing through the board right across the IC controlling the solenoids!
Because the interface board was mounted to the front panel without bond connections to the chassis, the temporary solution was simply to add a copper tape bond (diverting technique) between the board ground return and chassis upstream from the circuitry. Once that was in place, any induced ESD current was diverted back to the chassis before it could disrupt the circuitry. Problem solved!
Summary
I’ve used this technique for several years, helping clients solve their toughest ESD challenges. Best of all, it can easily be performed in-house where plenty of resources are available.
References
- Wyatt, “Verifying ESD Simulator Performance Using an Oscilloscope,” Tektronix.
- Henry Ott, Electromagnetic Compatibility Engineering, Wiley, 2008.
- Todd Hubing, www.LearnEMC.com
- Wyatt, “Troubleshooting ESD Failures Using an Oscilloscope,” Tektronix.
- Wyatt, “Trace ESD current paths with the HP 547A,” EDN.
