Get our free email newsletter

Toward Standardization of Low Impedance Contact CDM

Editor’s Note:  The paper on which this article is based was originally presented at the 41st Annual EOS/ESD Symposium, where it was awarded the Symposium Outstanding Paper in 2020. It is reprinted here with the gracious permission of the EOS/ESD Association, Inc.


The field-induced Charged Device Model (CDM) test method standardized in ANSI/ESDA/JEDEC JS-002 [1] is widely used for CDM qualification of integrated circuits. Because it relies on an air spark to initiate the stress, the pulse amplitude varies from zap to zap [2]. This discharge variation is increasingly significant as pre-charge voltage Vpre decreases [3]. 

Relay-based alternatives have been proposed to eliminate the variable air spark [2], [4]. Such “contact CDM” (CCDM) systems rely on transmission line pulsing and utilize 50 Ω coaxial cables and relays. It has been shown that 50 Ω systems generate pulses much wider than those of JS-002, but a better match can be obtained using lower system impedances. In [3], CCDM systems of 50 Ω, 25 Ω, and 11 Ω impedances were demonstrated. It was theorized that a 16.6 Ω CCDM system would provide the closest match to JS-002 in terms of waveform shape and the failure current (Ifail) thresholds generated.

- Partner Content -

A Dash of Maxwell’s: A Maxwell’s Equations Primer – Part Two

Maxwell’s Equations are eloquently simple yet excruciatingly complex. Their first statement by James Clerk Maxwell in 1864 heralded the beginning of the age of radio and, one could argue, the age of modern electronics.

In this work, a 16.6 Ω “Low Impedance” Contact CDM system (LICCDM) is demonstrated. This system complies with the newly published CCDM Standard Practice 5.3.3 [5]. The waveform shape and Ifail threshold generated during stress of a 32 nm test chip are compared against those of JS-002. It is shown that JS-002 produces non-monotonic peak currents (Ipeak) at low Vpre. LICCDM is monotonic and enables low voltage testing with higher accuracy. LICCDM and JS-002 are shown to exhibit the same Ipeak dependency on the effective device capacitance Ceff. Recommendations for merging JS-002 and LICCDM in a future standard are proposed.


A simplified hardware schematic of LICCDM is shown in Figure 1. The charge cable is charged and then quickly discharged through a relay. A transmission line pulse is delivered through a rise time filter to the device under test (DUT) by way of a coaxial cable connected to the pogo pin. A second coaxial cable is connected in parallel to the first and delivers the transmitted pulse to an oscilloscope. A 50 Ω resistor is also connected between the pogo pin and ground. The effective impedance of the system as seen by the DUT is hence 50 Ω || 50 Ω || 50 Ω = 16.6 Ω. Displacement current stresses the DUT during the pulse rising edge. The RC termination results in a slow decay of the falling edge of the incident pulse, thereby preventing dual-polarity stress to the DUT. By subtracting the transmitted voltage waveform from the incident waveform and dividing by the system impedance, the current through the DUT can be determined [3]. The pogo pin is in contact with the DUT both before and after the stress; hence, the only spark that occurs is within the relay.

Figure 1: Simplified hardware schematic of Low Impedance Contact CDM (LICCDM). Two coaxial cables – one for pulse delivery and the other for measurement – connect to the pogo pin along with a 50 Ω shunt resistor. The effective impedance of the system is thus 16.6 Ω.

The LICCDM test head is used on a Thermo Fisher Orion2 tester. The waveforms generated when stressing the large and small verification modules (coins) on both JS-002 and LICCDM are shown in Figure 2. Because the effective RLC models of the two testers are similar, the waveforms generated share close resemblance [3]. The LICCDM Vpre required to obtain a given Ipeak is approximately three times larger than that of JS-002. This is because the LICCDM Vpre is applied to the charge cable rather than directly to a field plate (JS-002). This charge cable Vpre is then divided as it travels through the transmission line network such that the actual voltage at the test head is approximately equal to the Vpre applied to the JS-002 field plate. 

Figure 2: Discharge waveforms from the large and small verification modules. The JS-002 is taken at 250 V, while the LICCDM voltage is scaled to match the peak current.

Test Chip Measurements

LICCDM and JS-002 were used to stress a test chip fabricated in a 32 nm CMOS process. A 37mm x 37mm LGA package was used. Some pins of this chip were known to fail below 250 V, so characterization at low voltages was conducted to determine an appropriate step size and starting voltage. 

Zap-to-zap variability

When characterizing a device to determine the CDM failure threshold, it is desirable to use a step size that is a small percentage of the threshold being resolved. For example, while a 50 V step size in Vpre may be adequate for resolving a failure occurring near 500 V, that same step size is relatively large when resolving a 125 V failure. However, it is well documented that air discharge CDM testing suffers from zap-to-zap variability arising from the variable nature of the spark [2], [3]. The step size must not be so small that the zap-to-zap variability in Ipeak is larger than the expected increment in Ipeak. Figure 3 shows the variation when stressing the small and large verification modules at various Vpre. A 25 V step increase in Vpre could result in no increase or even a decrease in Ipeak, as shown by the red arrow in Figure 3. Based on these data, testing with less than a 50 V step size would not be meaningful because Ipeak would be non-monotonic with Vpre.  

- From Our Sponsors -
Figure 3: The max, min, and average Ipeak measured during 50 zaps to the verification modules using JS-002. The red arrows indicate the non-monotonic behavior in Ipeak that is possible when incrementing Vpre by 25 V.

The variation measured on verification modules is a best case scenario: the modules have a large, uniform surface on which to discharge. When testing a package pin, Ipeak will also vary with pin shape and pogo pin alignment [6]. Figure 4 shows the Ipeak obtained from two units when measuring four pins of the test chip using JS-002. A single stress to each pin was used at a given Vpre. In between each voltage step the unit was removed for parametric testing and then re-aligned before incrementing Vpre. The re-alignment procedure introduces another variable in the Ipeak distribution. Despite 25 V increments to Vpre from 125 V to 175 V, Ipeak actually decreases in some cases (red arrows in Figure 4). Increasing Vpre from 175 V to 200 V causes more than a 60% Ipeak increase. These data indicate that even a 50 V step size is too small to avoid non-monotonic behavior; this makes it difficult to determine the true Ifail of the pin. 

Figure 4: Measured Ipeak from stress to the test chip at a given Vpre using JS-002. Data from single zaps to two units are displayed, both represented by a different symbol. A non-monotonic relationship with Vpre is exhibited (red arrow).

The same experiment is repeated using LICCDM to stress the test chip. Figure 5 shows a very repeatable, linear relationship between Ipeak and Vpre. Because contact is made with the pin before the stress is applied, there is no air spark. Furthermore, minor differences in pogo pin alignment have no impact on Ipeak. With zap-to-zap variation eliminated, a very fine step size in Vpre can be used. This enables the true Ifail to be extracted, even at low discharge currents and voltages. 

Figure 5: Measured Ipeak from stress to the test chip at a given Vpre using LICCDM. Data from single zaps to two units are displayed, both represented by a different symbol.

Pin location dependent variability

Sample waveforms from the test chip measurements are shown in Figures 6 and 7. Waveforms from the center of a package tend to be narrow, while those at the edge are wider and often have multiple peaks [7]. These variations are due to the parasitic elements of the discharge path within the DUT; charge from across the package takes longer to reach an edge pin than a center pin. LICCDM captures this natural source of variation which increases the likelihood of Ifail correlation with JS-002.

Figure 6: Test chip waveforms from a center package pin


Figure 7: Test chip waveforms from a pin near the package edge

Failure threshold comparison 

The Ifail of several different I/O circuits on the test chip were compared for both LICCDM and JS-002. Figures 8 and 9 show the Ifail of various output driver pins. In all cases the output driver itself was the anticipated location of failure. The Ifail levels generated by both testers are comparable in Figure 8. In Figure 9 some unit to unit variation is observed for both JS-002 and LICCDM. This makes it more difficult to compare Ifail levels. However, the thermally induced voltage alteration (TIVA) analysis in Figure 10 indicates that failures occurred in the driver transistors when stressed by both JS‑002 and LICCDM.

Figure 8: Ipeak measured on four pins from multiple units. Green indicates no failure, while red indicates damage.


Figure 9: Ipeak measured on eight pins from multiple units. Green indicates no failure, while red indicates damage. Unit to unit Ifail variation was more prevalent for this pin type, but the general trend aligns between both testers.


Figure 10: TIVA image of a pin from Figure 9 showing the same damaged regions of the driver after JS-002 and LICCDM stress

The test results from differential input pins with impedance matching termination resistors are shown in Figure 11 (all pins) and Figure 12 (CLKIN pins). The TIVA analysis in Figure 13 indicates failure in the termination resistor. Again, good correlation is observed between test types. The other pins in Figure 12 are general purpose input/output pins. No failures occurred on either test up to approximately 6 A.

Figure 11: Ipeak measured on six pins from multiple units. Green indicates no failure, while red indicates damage.


Figure 12: Ipeak measured on nine pins from multiple units. Green indicates no failure, while red indicates damage.


Figure 13: TIVA image of an input pin from Figure 11 showing damage in the termination resistor after JS-002 and LICCDM stress

Ipeak Dependence on Vpre, Ceff 

It was shown in [3] that CDM Ipeak can be captured as a single, continuous function Ipeak = f (Vpre, Ceff). In that work, the older “C101” air discharge test method [8] was used. This function is here applied to JS-002 (Figure 14) and LICCDM (Figure 15) using data taken on seven differently sized verification module coins. The area of these coins ranges from 4 mm2 to 1500 mm2. A good fit across Vpre and Ceff is achieved. Note that the plots represent the maximum Ipeak observed out of 50 zaps to each coin. While runt pulses are increasingly common and reduce the mean Ipeak at low Vpre during air discharge testing [3], the maximum Ipeak is very predictable down to single-digit Vpre. 

Figure 14: JS-002 Ipeak data (dots) from seven differently sized verification coins and the continuous function fit to the data (solid curves). The maximum Ipeak of 50 zaps is used to capture the worst scenario.

The models from Figures 14-15 are overlaid in Figure 16. The JS-002 standard has an Ipeak tolerance specified for two coin sizes at discrete “Test Conditions” (TCs) of 125 V and upward. These are indicated on the plot by solid black lines. The 1000 V, 250 V, and 125 V model curves from Figure 14 are thickened and shaded in Figure 16. The thickness represents the allowed JS-002 tolerance if it were extended across the entire Ceff range. While LICCDM (solid thin lines) is slightly less dependent on Ceff than JS-002, it can generate Ipeak within the allowed JS-002 Ipeak tolerance using a set Vpre. 

Figure 15: LICCDM Ipeak data (dots) from the same seven differently sized verification coins and the continuous function fit to the data (solid curves)


Figure 16: JS-002 model with Ipeak tolerance (shaded thick, from Figure 14) compared to LICCDM model (solid thin, from Figure 15)


While the LICCDM Standard Practice is a powerful CDM characterization tool, it cannot be used in lieu of JS-002 until it achieves Standard designation. This section describes the importance of investigating LICCDM for inclusion in a future Standard and what the next steps and considerations should be.

The need for LICCDM in a standard

This paper has highlighted several undesirable characteristics of air discharge CDM testing: zap-to-zap variation; sensitivity to pogo pin alignment; and non-monotonicity at low Vpre. These drawbacks will be increasingly impactful as design targets reduce below 250 V. Air discharge testing has other problems not addressed in this work. Packages with tight pin pitch are difficult to test with certainty because the spark from the pogo pin may strike any of the neighboring pins [9], [10]. Furthermore, the pogo pin may be larger than the pin being tested [9], [10]. Sharpening the tip can alter the onset of the spark generation and the corresponding waveform due to the corona effect [9]. 

LICCDM overcomes all of the above-mentioned problems because the pogo pin contacts the device pin prior to discharge. In addition to eliminating zap-to-zap variation, any uncertainty regarding which pin was stressed on a tight pin pitch package is also eliminated. A sharper, thinner pogo pin can also be used for testing small pins. This could conceivably be done at dimensions as small as the bare die level. The ability to test tight pitch, small dimension package pins will become increasingly important as package dimensions shrink to accommodate smaller form factors and faster signaling rates.

The need for more data

Given the decades-long history much of the industry has with air discharge CDM testing, it is highly desirable that any new test method replicate the stress and failure mechanisms of air discharge (i.e., JS-002 today). While this work and [3] have shown strong correlation between the two methods, a larger body of data is needed before LICCDM standardization. 

An important first step is an industry-wide round robin to examine the Ipeak vs. Ceff relationship of the two testers as was done in Figure 16. This can initially be done with verification module coins of varied sizes as was done in this work. JS-002 compliant testers from many manufacturers should be used along with multiple LICCDM tools. 

Next, device level testing on a range of product applications and technologies should be conducted at multiple companies using both test methods. Failure mechanisms, locations, and Ipeak should be compared. While many CDM-induced device failures are driven by Ipeak, others are driven by pulse rise time. Recent works have highlighted this as a potential source of miscorrelation when using relay-based alternative CDM test methods. In [11] it was postulated that a very fast-rising event occurs during air discharge testing as the capacitance between the pogo pin and the ground plane charges. This rapid event is not accurately measured by the disk resistor but was shown to be the likely cause of failure on a sensitive product.  Relay-based methods were only able to replicate this failure by generating sub-100 ps rise times. The same was true in [12]; a miscorrelation between air discharge and relay-based Capacitively Coupled TLP (CC-TLP) was only resolved with sub-100 ps rise times. LICCDM and CC-TLP can generate these fast rise times, but it complicates the hardware setup. Given that the sub-100 ps rise time is not accurately measured on JS-002 today, relay-based testers like LICCDM and CC-TLP actually offer a more accurate alternative. A broader product study can help the industry decide how crucial it is to replicate these rapid rise time events and what the correct waveform would look like.

Finally, the industry must decide what degree of correlation is required between LICCDM and JS-002 before LICCDM can be adopted. Given the drawbacks of JS-002 and the future direction of shrinking packaging technology and reduced CDM target levels, the benefits of LICCDM will likely outweigh infrequent miscorrelation. 

Framework for a future CDM test standard

An inclusive CDM standard was proposed in [3] that would allow a wide range of test methods to be used interchangeably. Such an approach required a unique Vpre adjustment for every DUT using a Ceff -dependent look-up table. The results in Figure 16 suggest that a simpler approach can be taken: LICCDM can achieve the existing JS-002 tolerance specifications without a DUT-by-DUT Vpre adjustment. If supported by round robin results, both air discharge and LICCDM (and possibly other methods) could be used interchangeably following nearly the same test procedure outlined in JS-002:

  1. Keep the existing JS-002 small / large verification module Ipeak + tolerance limits as-is. Add a third very small verification module (with corresponding limits) to be verified before testing very small devices. 
  2. Verify the tester by essentially following the JS-002 procedure. As is typical today with JS-002, the actual Vpre will not match the TC voltage. The software would apply a single scale factor to adjust Vpre such that the Ipeak requirements are satisfied for all three modules. For LICCDM, this scale factor would be larger (approximately 3x) because Vpre is applied to the charge cable.
  3. Specify the pertinent details of the waveform shape. It may be necessary to specify the rise time and pulse widths at multiple points (e.g., specify pulse width at 20%, 50%, and 80%). Product level correlation studies will inform these decisions.  
  4. Specify a TC above which either LICCDM or air discharge methods can be used. Below this TC, only LICCDM (or a similar relay-based tester compliant to #1 – #3 above) should be used to avoid significant variability. 
  5. Report the results in terms of the legacy Test Condition voltage. The Ipeak = f (Vpre, Ceff) continuous function could optionally be published to inform users of the expected Ipeak at any TC for a given Ceff. 


LICCDM shows strong correlation with JS-002 across a wide range of Vpre and Ceff. The Ifail generated using either JS-002 or LICCDM were equivalent on a 32 nm test chip. LICCDM eliminates a number of problems inherent with JS-002 air discharge testing, namely: zap-to-zap variation, non-monotonicity at low Vpre, and inaccurate testing of products with tight pin pitch or small pin dimensions. A simplified approach to a standard inclusive of air discharge and LICCDM is proposed, allowing either tester to be used interchangeably. Further data collection is needed at multiple sites and on a variety of products to determine the limits to apply to waveform parameters (e.g. rise time). 


The authors thank the ESDA/JEDEC CDM Joint Working Group for valuable discussion that shaped the direction of this work. The authors thank Thermo Fisher for manufacturing and loaning the LICCDM test head used in this work. 


  1. “Charged Device Model (CDM) – Device Level”, ANSI/ESDA/JEDEC, JS-002, 2018.
  2. R. Given, M. Hernandez, and T. Meuse, “CDM2 – A New CDM Test Method for Improved Test Repeatability and Reproducibility,” Proc. EOS/ESD Symp., 2010, pp. 359-367.
  3. N. Jack and T. Maloney, “Low Impedance Contact CDM,” Proc. EOS/ESD Symp., 2015.
  4. H. Wolf, H. Gieser, W. Stadler, and W. Wilkening, “Capacitively coupled transmission line pulsing CC-TLP—A traceable and reproducible stress method in the CDM-domain,” Proc. EOS/ESD Symp., 2003. 
  5. “Low Impedance Contact CDM as an Alternative CDM Characterization Method,” ANSI/ESD, SP5.3.3-2018.
  6. T. Brodbeck, K. Esmark, and W. Stadler, “CDM Tests on Interface Test Chips for the Verification of ESD Protection Concepts,” Proc. EOS/ESD Symp., 2007, 1A.1.
  7. J. Di Sarro, B. Reynolds, and R. Gauthier, “Influence of package parasitic elements on CDM stress,” Proc. EOS/ESD Symp., 2013, 9A.3.
  8. “Field-induced charge-device model test method for electrostatic discharge withstand thresholds of microelectronic component,” JEDEC, JESD22-C101F, 2013.
  9. Industry Council on ESD Target Levels, May 2016, “White Paper 2: A case for lowering component level CDM ESD specifications and requirements.”
  10. R. Ashton, M. Johnson, S. Ward, “CDM Testing of Small Integrated Circuits,” In Compliance Magazine, June 2010.
  11. D. Johnsson, K. Domanski, and H. Gossner, “Device Failure from the Initial Current Step of a CDM Discharge,” Proc. EOS/ESD Symp., 2018.
  12. J. Weber et al., “Comparison of CDM and CC-TLP Robustness for an Ultra-High Speed Interface IC,” Proc. EOS/ESD Symp., 2018.

Related Articles

Digital Sponsors

Become a Sponsor

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.

Get our email updates

What's New

- From Our Sponsors -

Sign up for the In Compliance Email Newsletter

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.