Testing

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!

Electromagnetic disturbances can greatly influence the performance of equipment and the functional safety of systems. Consider the current problems we hear in the news with unintended acceleration in some vehicles. While this complication’s true cause may never be determined, analysts have theorized that electromagnetic disturbances could play a large role. Due to the amount of electronics and ever changing technologies found in today’s automobiles, unintended acceleration is only one of many examples of unwanted anomalies that could occur due to an EMC issue. Automakers are faced everyday with the risk and associated liability that could come with a problem such as this once the vehicle is on the street with the consumer. That risk is why the automakers over time have had to develop specific test standards that relate to the EMC concerns of their vehicles and enforce their suppliers to meet them by way of specific test plans. The automotive industry is just one example of how EMC can relate to the functional safety of a product as guided by IEC TS 61000-1-2: 2008.

In earlier articles in this publication we have discussed the charged device model (CDM) testing of small devices. In the first article we demonstrated that the peak current for small devices does not become vanishingly small.¹ The commonly held belief of vanishing current for small devices was shown to be an artifact of measuring the current with the 1 GHz oscilloscope² specified in the JEDEC CDM standard.⁶ The second article explained various ways to make CDM testing of small devices more reliable with the use of small surrogate packages, or the use of templates to hold the device during testing.³ In this article we will show how insight can be gained into the CDM testing of small devices using a simple three capacitor circuit model.^{4, 5}

The 21st century as we know it, truly reflects the age of technology. Every aspect of life today is encompassed by the use of some sort of microprocessor based electronics intended to simplify tasks, to improve processes, and improve efficiency. Electronics are used to communicate with loved ones, manage finances, fly aircraft, even save lives. As greater advances in technology are achieved, electronics are found controlling more important safety critical functions at an exponential rate. Although electronics have provided us with obvious benefits, the increasing reliability on electronics has elevated our vulnerability to the effects electromagnetic pulses.

Wireless alliances like Wi-Fi and ZigBee certify wireless devices for interoperability which to the end user provide a confidence level of smooth operation between these devices from different manufacturers. For instance this level of interoperability is necessary (but not sufficient) to ensure communications on WLAN Wi-Fi segments containing an Access Point (AP) and a number of wireless client cards. The same concept applies to ZigBee networks where interoperability gives a confidence level for ensuring operation of devices such as a light bulb and a switch, an RF4CE remote control and paired TV, DVD player or set top box, but also insufficient to assure seamless operation of the network over time and under variable environmental conditions especially in demand-response time critical scenarios.

Integrated circuits are classified for ESD robustness using a variety of tests. The most popular tests are Human Body Model (HBM) and Charged Device Model (CDM). These two ESD classifications are intended to indicate how well a circuit will survive ESD stresses in manufacturing environments which include basic ESD controls. HBM is the oldest of the ESD tests, but factory ESD control experts generally agree that CDM is the more important test in modern, highly automated, assembly operations. The amount of stress for CDM scales with the size of the device. For that reason “conventional wisdom” on CDM has often stated that you don’t need to test very small integrated circuits because the peak currents get vanishingly small. In last month’s article for IN Compliance [1] we presented an article showing that the peak current for very small devices does not become vanishingly small as often thought. Measurements with a high speed oscilloscope demonstrated that peak currents remain surprisingly high even for very small devices although the width of the pulse gets very narrow. In the past these high peak currents were missed due to the use of 1 GHz oscilloscopes as called for in the standard for the field induced CDM test [2], the most popular form of CDM testing.

The railway environment is generally regarded as a “severe” electromagnetic environment. For an electrified railway, Megawatts of power are required to be converted into the propulsion of trains in order to transport passengers or freight from one destination to another. The railway presents a complex electromagnetic environment made up of many systems including signalling, traction, telecommunications and radiocommunications.

Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.

Anyone who has worked in Quality or Reliability in a large corporation knows that developing and presenting credible failure cost information can be difficult. This is particularly true for ESD, where the events are invisible and not nearly as well understood as other more obvious classes of failure, such as mechanical or contamination. The “real” cost of ESD can be a hot topic of discussion each year when program budgets are being developed for manufacturing and R&D programs. The challenge is that every year there are new high-level people in the financial and planning organizations who are not technical experts and who are asking hard questions about the justification for the ESD investment. In years when revenue is down, the questions become more difficult and better evidence is often demanded. The author was directly involved in this process for 15 years, starting in 1986. At the time the following quote was a part of many ESD funding discussions; “… in the electronics industry, losses associated with ESD are estimated at between a half billion and five billion dollars annually.” The exact original reference for this assertion has been lost, at least to this author. Nonetheless it was used many times over the next few years in presentations to the corporate check writers. Furthermore, during research for background information for this article, the exact same quote appeared (unattributed) in an article from 1992 [1] and in a book published in 2006 [2]. Needless to say, a well-stated assertion of value can go a long way – at least in trade literature. However, this author can also report that the usefulness of this, inside the corporation, eroded much faster. By 1990, a well-known director in Bell Labs said; “… that was then… I think this problem has been solved!” Many of us would scoff at such a declaration, knowing full well that ESD problems were continuing to occur. However, the directors’ challenge was an appropriate one. His experience came from the semiconductor process world where he had seen significant ESD sources eliminated and device thresholds (albeit HBM only) steadily increase. Corporations would like their investments to be justified by more timely and relevant data and observations.  They ask, “What is the “real” cost?”

Being first to market is what enables a company to capture the rewards of an efficient product development program. Among the benefits of such a program is a greater return on investment (ROI), triumph over the competition and increased shareholder’s satisfaction. However, there are pressures such as a slow growth domestic economy, a growing global marketplace and a highly competitive market environment.