ESD Testing

With the inventions of the transistor in 1948 and the Integrated Circuit in 1958, and the utilization of these major breakthroughs in the development of computers and other electronic devices, industry began to worry about and to design components and end-products that could survive the discharge of electrostatic discharges to chips, printed circuit boards, and final packaged-products.

Released in May of 2011, GR-1089-CORE Issue 6 Electromagnetic Compatibility (EMC) and Electrical Safety requirements for Network Telecommunications Equipment has undergone a number of technical changes. We look at its substantial modifications and the potential impact on previously certified products.

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!

In earlier articles in this publication we have discussed the charged device model (CDM) testing of small devices. In the first article we demonstrated that the peak current for small devices does not become vanishingly small.¹ The commonly held belief of vanishing current for small devices was shown to be an artifact of measuring the current with the 1 GHz oscilloscope² specified in the JEDEC CDM standard.⁶ The second article explained various ways to make CDM testing of small devices more reliable with the use of small surrogate packages, or the use of templates to hold the device during testing.³ In this article we will show how insight can be gained into the CDM testing of small devices using a simple three capacitor circuit model.^{4, 5}

Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.