ESD Testing

Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has...

Historical Background  CDM is an important model for ESD qualification. The well-known CDM refers to...

CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.

The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.

Should I use the pin combinations in Table 2A or Table 2B per Human Body Model (HBM) standard JS-001?

Updates to Past CDM Open Forum Questions

It is no trivial matter to properly interpret system level test results on high-speed boards. Board manufacturers (OEMs) assess the ESD robustness of their system by means of gun testing, not always in accordance with the IEC standard.

How can we provide a quantitative measure of ESD robustness but control the rising test times while preventing major overstress and wear out from thousands of ESD strikes per IC?

The charged device model describes the electrostatic discharge (ESD) event that occurs when an integrated circuit (IC) is rapidly charged or discharged through a single pin to a metallic surface.

The International Electrotechnical Commission (IEC) has released IEC 60749-28:2017