ESD Testing

A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.

This blog explains CDM ESD testing using the field-induced (FI) method, which is important for semiconductor manufacturers. It covers building a CDM-FI tester, waveform details and verification, and qualification nuances. 

Leakage or touch current tests for electrical shock protection is mandated by safety standards in the process of issuing a safety certification for various electrical products. In this article, electrical shock sensation experiments were conducted for a complex waveform composed of a combination of 60 Hz and a higher frequency sinusoidal signal.

The behavior of ultra-high-speed interfaces is complex, involving fast-rise time waveforms and on-die transient phenomena that cause device failure at lower CDM levels.

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

To provide in-depth coverage of ESD testing methods, in this article, we look at another type of ESD testing based on the “Human Body Model” (HBM) method of ESD testing.

Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, I_fail, and I_peak vs. C_eff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.