Columns

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

History is very telling in influencing the trajectories of product safety and liability. To get the details, we turned to insight from Doug Nix, Managing Director of Compliance inSight Consulting and lead author of the Machinery Safety 101 blog. Read the interview with Nix for context on how the past has shaped the ideology and approaches that we employ today.

Operating my personal document shredder crashes my digital TV set-top box, although it is 5 metres away. Toggling the on/off button on the set-top box restores normal operation. 

This is the seventh column in a series devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters, and employ different ground techniques .

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

This article focuses on PCB layout considerations and the design of the reference return paths for the one- and two-layer boards.

If you really want to know whether your footwear and flooring are working together, measure the resistance from the wearer via footwear and flooring to earth (ground).

In the kitchen we have a radio/tape/cd and recently the tapes have been playing with very poor sound quality.

This is the fifth article in a series of articles devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters, and employ different ground techniques.

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.