Columns

USB-C's high-speed data lines need robust ESD protection, but TVS device placement matters critically. New research reveals why positioning protection behind AC coupling capacitors—not in front—delivers superior IC protection for sensitive SuperSpeed applications.

Full-wave EMC simulation tools are powerful — but often too slow, too costly, and too complex for real-world troubleshooting. Dr. Min Zhang makes the case for free SPICE-based tools, walking through three field scenarios where quick models helped isolate failures, validate test setups, and guide next-generation designs.

This is the second of seven articles devoted to the topic of shielding to prevent electromagnetic wave radiation. This article discusses the normal incidence of a uniform plane wave on a solid conducting shield with no apertures.

Traditional Charged Device Model testing falls short for bare dies in 2.5D/3D devices. With discharge currents reaching 500 mA at just 5V, existing methods can't handle the unique challenges of testing unpackaged components. CCTLP emerges as a promising alternative for reliable low-voltage testing.

This is the first of seven articles devoted to the topic of shielding to prevent electromagnetic wave radiation. The results presented here are valid under the assumption of a uniform plane wave with normal (perpendicular) incidence on a boundary between two media.

A new version of Technical Report TR18.0-01-25 (TR18) on ESD Electronic Design Automation (EDA) Checks by the ESD Association’s Working Group 18 is about to be released. This article, divided into Part 1 and Part 2, provides guidelines for the EDA industry and the ESD design community for establishing a comprehensive ESD verification flow to address the ESD design challenges of modern ICs.

This column examines inductor impedance evaluation using S₂₁ parameters with network analyzers. Comparing two-port shunt and series methods across multiple inductors, it concludes that the two-port series method provides significantly more accurate measurements when compared with manufacturer data.

This article introduces an upcoming Technical Report (TR18) from the ESD Association on Electronic Design Automation checks. It details integrated ESD verification throughout IC design phases, covering schematic-based topological checks and layout-based verification to ensure comprehensive ESD protection in modern circuits.

A routine radiated emissions case took an unexpected turn when slow I/O lines started radiating 100 MHz harmonics—pointing to a deeper power distribution network problem. Dr. Min Zhang traces the root cause and the PDN fixes that made the ferrite beads unnecessary.

This article introduces ANSI Z535.7, a new standard released in late 2024 addressing product safety information in electronic media. It complements existing ANSI standards by providing guidelines for digital formats, helping manufacturers create consistent safety messaging across both physical and electronic platforms.