Columns

In this article, we investigate the impact of a guard trace on crosstalk reduction and present measurements taken with the latest‑generation PCB, both in time and frequency domains.

This article is the first of a two-article series devoted to the topic of crosstalk between PCB traces. In Part 1 of the series, we vary circuit topology, i.e., the distance between traces and the distance to the ground plane.

The article discusses ESD protection challenges for RF switches in SOI technology. It examines the self-protection mechanism, proposes a behavioral model to simulate ESD response more accurately, and explores predicting failure current levels critical for reliable ESD design.

We are proud to carry on the tradition of sharing Banana Skins for the purpose of promoting education for EMI/EMC engineers.

This article presents the derivation of the radiated far fields from a Hertzian dipole antenna above the ground plane using image theory.

It is now well known that testing for CDM ESD evaluation is becoming a bigger challenge. An alternate approach called capacitively coupled transmission line pulsing (CCTLP) offers advantages over standard field-induced CDM testing.

In large systems, such as big cabinets housing numerous electronic components, employing the near-field probe method can be time-consuming and, depending on the voltage level, potentially unsafe (for instance, when dealing with high-voltage circuits requiring isolation). In such scenarios, an alternative approach is necessary.

The Banana Skin columns were compiled by Keith Armstrong, of Cherry Clough Consultants Ltd, from items he found in various publications, and anecdotes and links sent in by the many fans of the column.

The authors evaluate the impact of capacitors and trace length on conducted emissions.

The ESDA technology roadmap is written to support and guide the daily work of ESD and latch-up experts in the worldwide industry and academia.