Hot Topics in ESD Archives - In Compliance Magazine

Understanding Embedded On-Chip ESD Detection, Part 1

ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.

CDE Modeling Using Star-Tree Impedance Networks for USB2 Cable

Simple star-tree networks, as shown here for USB2, should have wide applicability for cables carrying fast signals.

Can Electrostatic Discharge Design Problems Be Solved with Electronic Design Automation Tools Alone? Part 2

In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.

Can Electrostatic Discharge Design Problems Be Solved with Electronic Design Automation Tools Alone? Part 1

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

The Dilemma Between Customers and Suppliers on EOS Failures

During the last four decades, damage to devices from electrical overstress (EOS) has confounded both IC suppliers and customers. The Industry Council on ESD Target Levels investigated numerous EOS root causes and established a white paper on the subject, JEP174 [1].

The Transistor: An Indispensable ESD Protection Device – Part 2

In this article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.

Updated Trends in Charge Device Model (CDM)

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

Challenges of Designing System-level ESD Protection at the IC Level, Part 2

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).

ESD Challenges in 2.5D/3D Integration

2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.

A Look Into Generator Waveforms: Do They Meet the IEC 61000-4-2 Waveform Specification?

This article explores the waveform specifications called out in the IEC 61000-4-2 standard.