ESD Co-Design for High-Speed SerDes in FinFET Technologies

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

Ohm’s Law Also Applies to ESD‑Induced Heat Pulses

Heat flow analysis for semiconductor ESD situations can be approximated to one dimension, and then captured with a generalized Ohm’s Law using a complex impedance. Methods can include time-dependent electrothermal pulses and feedback due to self-heating, with solutions readily carried out on any desktop computer.

Caster Contact: The Achilles Heel of ESD Floors

A fully functional ESD floor prevents static generation and provides an effective path to ground for personnel and equipment. Many conductive and dissipative floors meet STM 7.1 resistance parameters in ANSI/ESD S20.20 but fail to provide adequate electrical contact for grounding equipment with conductive casters and drag chains.