Printed Circuit Boards

The board stackup is probably the most essential piece for ensuring a successful PCB design. Modern high-speed busses require controlled-impedance traces, and whether you are using a simulation tool, a simple calculator, or the back of a napkin, you need to understand your manufacturing process to correlate your impedance calculations. This ensures that your trace widths and dielectric heights match what will actually be manufactured, and eliminates last-minute design changes.

There may be a better use for PCB planes than to just distribute power, namely to provide shielding.

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!

Each year the IEEE Electromagnetic Compatibility Society sponsors a Best Student Paper competition as part of the IEEE International Symposium on EMC.  The contest is administered by the Educational and Student Activities Committee (ESAC) of the Society.  For the 2010 Symposium 33 student papers were submitted, the largest number in recent memory.  An ESAC panel reviewed and ranked the submissions based on technical contribution, accuracy, and clarity.  It always proves to be a challenge to select a single winner from the many fine papers covering many diverse aspects of EMC that are received.  The paper selected for 2010 use modal decomposition to derive a transmission line model for printed circuit board vias that can be implemented in circuit simulators.  The new model has a significantly faster computation time than that of a full-wave simulator while giving results that are in good agreement.  The practical benefit is an improved facility for of the design and optimization of high speed digital circuit boards for both signal integrity and EMC compliance.

In the past EMC Engineers have relied on metallic enclosures to contain electromagnetic fields and meet radiated emissions limits in military and consumer products. Modern commercial electronics products typically use molded plastic enclosures since they are considered to be aesthetically more pleasing than a metal enclosure, but also to save weight and cost.

This paper describes how to remove the measurement artifacts caused by discontinuities in high frequency S-parameter data caused by the test connectors on the Printed Circuit Boards (PCBs) and cables. The frequency domain S-parameters are converted to the time domain to get the impulse response. Time domain gating is then used on this impulse response to remove reflections due to end connectors and/or other discontinuities. The gated impulse response is then transformed back to the frequency domain. The final result is a much improved S-parameter data set with unwanted resonance removed, allowing the PCB trace or cable loss to be determined.