Design

Implementing a process of EMC compliance for a specific project is much more than simply ensuring that the design engineers follow a long list of “do’s and don’ts” in the form of EMC design rules. Following this process will reap benefits when EMC performance is evaluated at the end of the design process.

A careful review of empirical research, multiple ESD standards, and return on investment provides a strong case for evaluating the installation of ESD flooring in server rooms and data centers.

Part 1 of this two-part article explores some basic rules for terminating cable shields. Part 2 of the article will appear in our October 2022 issue and will summarize the results of recent testing conducted by the author on the shielding effectiveness of screened cables up to 2.8 GHz

Should the reference (i.e., ground) plane be split into two separate sections and a ferrite bead installed between them to prevent unwanted radio frequency emissions? Let’s examine why this practice is not a good idea and should be avoided at all costs.

The selection of component values for common mode filters need not be a difficult and confusing process. The use of standard filter alignments can be utilized to achieve a relatively simple and straightforward design process, though such alignments may readily be modified to utilize pre-defined component values.

There is often confusion about the interaction between IC-level component ESD protection and the appropriately required system-level ESD protection strategy.

In this column, the author offers a brief summary of a more systematic approach for using ferrite cores on cables. This summary can serve as a “ferrite core checklist” for design and test engineers.

This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

Discover the most important post-layout elements when selecting a SI/PI software simulation package.

This is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.