Design

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.

This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD behavior of the Common Mode Choke (CMC).

This is the second article of a two-article series devoted to the return current distribution in a PCB microstrip line configuration.

This paper provides a comprehensive study on how to mitigate desense with the change in the spectrum distribution by tuning the duty cycle of the interfering clock. Measurements conducted on a real cellphone showed a 10 dB suppression of desense for certain TX bandwidth condition.

This is the first article of a two-article series devoted to the return current distribution in a 2-layer FR-4 PCB microstrip line configuration with a solid reference plane.

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

Many years ago, the author experimented on a metal enclosure of one of his company’s main products. The experiment involved placing an electric field probe inside the empty metal enclosure (no electronics inside) and applying 10 V/m using the IEC 61000-4-3 radiated RF immunity test system.

The Standards Council of Canada (CSA) has published a new National Standard applicable to...

The FAA has published requirements that require testing for all battery devices that are a part of the aircraft itself.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.