ESD Control

This column outlines the steps to consider when embedding ESD detection capabilities into your system and overall design flow.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.

In this article, we describe how wireless measurements of human body voltage can be made, and why they are important for ESD managers.

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.

This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD behavior of the Common Mode Choke (CMC).

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).