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The Many Aspects of Semiconductor Reliability with Impact on ESD Design

Many articles published in In Compliance focus on ESD design and testing methods. But there is a lot more to semiconductor reliability. ESD reliability is based on the understanding of the high current behavior of protection devices. Protection designs are implemented in the IC to meet the ESD targets. This approach is not feasible for most of the other semiconductor reliability phenomena. In contrast to ESD, the actual understanding and definition of semiconductor reliability for field applications is less precise. It requires the understanding of device physics and reliability models. These models are mostly established and allow with some confidence to predict the IC device lifetime during field applications. In this article, we will have a look at different reliability phenomena and models and their contribution to the overall semiconductor reliability. We specifically cite only three representative references here [1-3] although the literature has an immense amount of work on the different reliability aspects, especially exhaustively covered by the technical papers at the International Reliability Physics Symposium for the last five decades.

The major reliability concerns for CMOS technologies include Hot Carrier Injection (HCI), Gate Oxide Reliability (GOX), Electro-migration (EM), Negative Bias Temperature Instability (NBTI), and Latchup (LUP). A more uniquely different topic is Electrical Overstress (EOS). EOS is often caused by misapplications as reported by the white paper from the Industry Council [4]. For example, the maximum voltage applied on the supply pin exceeds its absolute maximum voltage rating or AMR. This can cause latchup and high thermal stress and eventually lead to an EOS damage.

Figure 1 links all of these in a visual manner. ESD reliability is purposely placed at the centre although this is not necessarily true for every IC product development. In fact, often ESD is addressed after a reliable process technology is established. As shown in the figure the reliability issues are all interconnected to both EOS and ESD although not necessarily in the same manner or to the same extent. Each of these reliability aspects have to be first considered separately before the connections to ESD and/or EOS can be understood.

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Figure 1: Interrelations between the various IC reliability effects

HCI (noted as CHC in the figure) is related to degradation of transistor conductance during long-term operation caused by hot electron injection near a high field drain junction in a transistor. HCI can be mitigated with engineering of the drain junction with lightly doped drain (LDD) or graded junction implants that reduce the drain electric field. This improvement is a result of reduced peak substrate current ISUB. Incidentally, ISUB in turn plays a role on ESD and Latchup designs because of its impact on the parasitic bipolar transistor.

GOX reliability includes two issues: GOX breakdown and time-dependent-dielectric-breakdown (TDDB). GOX breakdown occurs when the applied voltage (or electrical field) exceeds the dielectric strength of the GOX. It can also suffer from a slow breakdown during its lifetime at normal operating voltages. This phenomenon is known as TDDB. Both of them are impacted by ESD stress either in magnitude, duration or in repetition. Therefore, ESD is a serious concern for GOX reliability and the oxide breakdown voltage is a main design input during ESD protection design.

NBTI is a serious concern for CMOS technologies starting at the sub-500nm nodes and for PMOS transistors that mostly operate in gate-to-source voltage mode. It can lead to a degradation of the trans-conductance. Consequently, if a large PMOS transistor is used as an ESD clamp in MOS conduction mode it should be characterized for NBTI effects.

The parasitic interaction between NMOS and PMOS can form a lateral pnpn device or thyristor. A turn-on of this thyristor during normal IC operation can lead to LUP. Ironically, this pnpn is also used as a well-known ESD protection device, the Silicon Controlled Rectifier (SCR). The substrate also plays a critical role for Silicon on Insulator (SOI) technologies developed to mitigate LUP in very advanced technology nodes. The use of the buried oxide in SOI technologies can have an adverse impact on ESD due to self-heating effects.

EM is a result of current conduction with a high current density through metal lines. It is strongly impacted by the interconnect technology. During ESD and EOS events a metal line temporarily heats up. This can lead to a degradation of its EM lifetime. To avoid these effects, a reliable ESD design requires sufficient wide metal lines. Both ESD and EOS can also cause contact burnout or via migration. Technology process changes with barrier metals such as Titanium or Tungsten are developed to prevent contact spikes and increase the reliability of these interconnects.

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There are also reliability issues at IC package level. Materials, package type, electrical bias, operation temperature and environmental conditions during normal operation of the IC can affect the corrosion of metals and mechanical stress in the package during its lifetime.

In conclusion, there are various reliability issues in semiconductor devices. In contrast to ESD, most reliability issues are not solved by design but solely with the help of predictive reliability models. Reliability issues need to be continuously addressed during technology development as technologies further advance into novel transistor structures such as FinFETs and Multi-gate devices.

References

  1. C. Hu et al., “Hot-electron induced MOSFET degradation – Model, monitor, and improvement,” IEEE Tran. Elec. Dev., ED32, P. 375, 1985.
  2. A. Ille, W. Stadler, A. Kerber, T. Pompi, T. Brodbeck, K. Esmark and A. Bravix, “Ultra-thin gate oxide reliability in the ESD time domain,” EOS/ESD Symposium, pp. 285-294, 2006.
  3. K. Banerjee, A. Amerasekera, and C. Hu, “Characterization of VLSI circuit interconnect heating and failure under ESD conditions,” Reliability Physics Symposium, 1996, 34th Annual Proceedings, IEEE International, pp. 237-245.
  4. JEDEC Document, JEP 174, “Understanding Electrical Overstress – EOS.”

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