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The ESD Association Technology Roadmap

The ESDA technology roadmap is written to support and guide the daily work of ESD and latch-up experts in the worldwide industry and academia. At the same time, it is intended to provide a glimpse into the future ESD thresholds of semiconductor devices and their impact on ESD control practices. It also presents current and future technical challenges in ESD and latch-up. With their expertise vision, the ESDA Advanced Topics Team has completed the most recent edition, published in January 2024 [1]. In this article, we want to highlight some of the changes and look at one key trend in advanced packaging.

ESD Target Level

The evolution of CDM target levels was previously summarized in [2]. As technologies further advanced, it became necessary to reduce CDM target levels from 500 V to 125 V for ultra high-speed IO applications. However, depending on the IC design functions, the achievable level can be 500-125V.  Looking forward to the next decade and beyond this can be even below 125 V. Figure 1 shows the device ESD design sensitivity trends based on the main standards used for the ESD qualification at component-level: Human Body Model (HBM) and Charge Device Model (CDM). The shown sensitivity limits are a projection by engineers from leading semiconductor companies. For both qualification standards, no changes are expected until 2030. The current target level for HBM is kept at 1kV and for CDM at 250V.

Figure 1: HBM (left) and CDM (right) roadmap.

In practice, the achievable CDM protection level depends on the IO design or type and on package size effects. Larger packages will experience higher discharge currents at a given stress voltage level. Figure 2 illustrates the impact of application and IC packaging on the achievable CDM robustness for packaged exposed “external” pins and “internal” pins of 2.5D and 3D integrated ICs. In the RF space, there is often a delicate balance between CDM robustness and RF performance. As higher bandwidth RF applications become more widespread in the market, the achievable CDM protection level is likely further decreasing. For internal pins, the provided range is based on the area constraints for internal IO that only allow the use of very little to no additional area to enable minimal CDM robustness.

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Figure 2: Combined projected effects of IO design and IC package size on achievable CDM protection level

ESD Testing

Because of the larger variability when applying low-stress levels and decreasing pin pitches, the commonly used field-induced CDM testing reaches its limitations. Contact CDM testing methods allow the reliable application of low CDM stress levels even to small pin pitches. Two contact CDM stress methods, low impedance-contact CDM (LICCDM) and capacitively coupled TLP (cc-TLP), are currently evaluated by the ESDA JEDEC CDM Joint Working Group. Both methods allow the application of low CDM stress levels and can be used to stress small pin pitches. Thereby, cc-TLP systems have been used for a much longer time compared to LICCDM setups and showed a good correlation with CDM results in many studies.

Outlook

The scaling of CMOS technologies continues, moving from FinFET to nanowire- or nanosheet-based device architectures. Another driver will be the broad use of compound semiconductors such as Gallium Nitride or Silicon Carbide, particularly in energy conversion. This includes the application of photonic technologies to enable the required huge data bandwidths of the digital society. Electronic Design Automation (EDA) tools for design verification will be able to support the ESD and latch-up protection design even more. Always-increasing computational power and new machine learning methods will allow us to simulate and verify complex IC designs.

A strong push will be seen in advanced packaging where separate dies or chiplets that may come from different technologies are connected in a single package. What are the ESD Challenges associated with this advanced packaging? In the next few years, the density of micro bumps increases significantly. It is enabled by reducing the bump pitch from more than 25µm to less than 10µm. A higher die-to-die interface density requires reducing the minimum CDM level for die-to-die interfaces (Figure 3). This is because the typical area allocated to ESD protection of external pins is not available for these internal interconnects [3] and is not necessary for manufacturing. CDM target levels for die-to-die interfaces described in the literature are below 100V [3], for which ESD controls are adequately described by S20.20. Below the CDM sensitivity level of 100V, there are no means of controlling ESD; each case must be carefully analyzed to determine the ESD risk and mitigations necessary to ensure manufacturability. Developing ESD control standards below 100V is a critical need for the industry to improve this situation.

Figure 3: Roadmap of CDM target level of Die-to-Die Interfaces [4]

Summary

The ESDA technology roadmap is a guiding document for the daily work of ESD and latch-up experts in the worldwide industry and academia. In this article, we highlighted the ESD target levels and focused on one major trend in our industry. The work on the roadmap will continue. The next edition is already in the works and will be published by the next EOS/ESD Symposium in September 2024.

References

  1. https://www.esda.org/standards
  2. C. Duvvury and A. Righter, “Evolution of Charged Device Model ESD Target Requirements,” In Compliance Magazine, February 26, 2021.
  3. Dina Medhat et al., “A Programmable Checker for Automated 2.5-D/3-D IC ESD Verification,” 2021 IEEE Transactions on Components, Packaging, and Manufacturing Technology.
  4. White Paper 2: A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces, 2023.

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