Souvick Mitra

The Impact on ESD Risk of AI on Silicon Fabrication and the Implications of Increasing Memory Stacks

This column explores the significant impact of artificial intelligence on advancements in silicon fabrication, focusing on the development of high bandwidth memory (HBM) and associated die-to-die(D2D) electrostatic discharge (ESD) protection challenges.

What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.

Impact of 3D IC Design on ESD Protection

What is 3D Integration and what is 3D IC? If we rewind three decades, back...

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