Scott Mee

Before you can calculate shielding effectiveness, you need to know whether your material qualifies as a good conductor — and that's where loss tangent comes in. This deep dive connects the math to the physics, from plane wave propagation to practical near- and far-field shielding formulas.

Via placement and trace geometry significantly affect decoupling capacitor performance. This final installment of a three-part series presents conducted emissions measurements across six PCB via topologies, revealing how distance from the power-ground plane pair and via spacing impact EMC results.

Conducted emissions testing on custom PCBs shows how moving a decoupling capacitor farther from an IC can increase emissions across multiple frequency bands. Using CISPR 25 methods, this study compares capacitor placements and via topologies to reveal how distance and inductance shape PDN behavior.

Discover how a unique collaboration between Grand Valley State University and E3 Compliance creates exceptional learning opportunities in EMC and high-speed electronics. Learn how students gain hands-on industry experience through co-op programs, research projects, and real-world testing, preparing them for successful careers in electromagnetic compatibility.

This is the second article of a two-article series devoted to the return current distribution in a PCB microstrip line configuration.

This is the first article of a two-article series devoted to the return current distribution in a 2-layer FR-4 PCB microstrip line configuration with a solid reference plane.

This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

This is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

This is the first of three articles devoted to the design, test, and electromagnetic compatibility (EMC) immunity evaluation of multilayer PCBs containing analog circuitry. In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques.

This is the 10th and the final article in a series of articles devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters and employ different ground techniques.