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The Useful Mirror Technique

The mirror technique is a very old technique to be used with PCBs when failing in radiated EMC tests. An easy solution to avoid changes in layout if the technique can be applied to your product.

Do Measurements Validate Simulations?

It is very common for people doing simulations to make a measurement of a similar set up to validate the simulation. This is a reasonable precaution since modern simulation tools will give a very accurate answer to whatever question it is asked.

Decreased CDM Ratings for ESD-Sensitive Devices in Printed Circuit Boards

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!