Get our free email newsletter

peter de jong

ESD Co-Design for High-Speed SerDes in FinFET Technologies

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

Qualification of Interface IP for Charge Device Model Based on Peak Current

The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.

Digital Sponsors

Become a Sponsor

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.

Get our email updates

What's New

- From Our Sponsors -

Sign up for the In Compliance Email Newsletter

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.