pcb

This is the second article of a two-article series devoted to the return current distribution in a PCB microstrip line configuration.

This is the first article of a two-article series devoted to the return current distribution in a 2-layer FR-4 PCB microstrip line configuration with a solid reference plane.

Most EMI issues are caused by a resonance that is excited somewhere in the system. It may be a resonance of a cable acting as an antenna or a heatsink energized by the power electronics switches bolted to it, becoming a good radiator. In this article, we look at the indicators that signal the presence of structural resonances and provide techniques for fixing the EMI issues. Practical case studies are presented to demonstrate the techniques.

Should the reference (i.e., ground) plane be split into two separate sections and a ferrite bead installed between them to prevent unwanted radio frequency emissions? Let’s examine why this practice is not a good idea and should be avoided at all costs.

This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

This is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.

This is the first of three articles devoted to the design, test, and electromagnetic compatibility (EMC) immunity evaluation of multilayer PCBs containing analog circuitry. In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques.

This article discusses the current distribution for the stripline configurations.

This article discusses the distribution of a PCB return current underneath top trace for the microstrip configuration. Next month’s article will discuss the distribution for the stripline configurations.

This article provides insight into how shielding is used in product development, in particular the effectiveness of shielding when it is applied at the PCB level.