PCB layout

Via placement and trace geometry significantly affect decoupling capacitor performance. This final installment of a three-part series presents conducted emissions measurements across six PCB via topologies, revealing how distance from the power-ground plane pair and via spacing impact EMC results.

Changing enclosures, PCB layouts, component sources, or software doesn't mean the schematic changed—but it may mean your EMC certification did. This installment of Standards Practice breaks down which hardware modifications trigger the need for retesting, and why skipping it can be a costly mistake.

Discover how PCB layout choices can dramatically alter S‑parameter measurements of high‑speed ESD protection devices—especially in the femtofarad range. Through 3D EM simulations and real‑world testing, this article reveals why accurate modeling and optimized test boards are essential for reliable high‑speed performance.

When your circuit misbehaves with unexplained noise and jitter, you're facing electromagnetic coupling. This practical guide walks engineers through identifying whether problems stem from differential or common mode issues, near-field or far-field effects, and provides a systematic debugging workflow to isolate sources, paths, and receivers—getting your design back on track.

A routine radiated emissions case took an unexpected turn when slow I/O lines started radiating 100 MHz harmonics—pointing to a deeper power distribution network problem. Dr. Min Zhang traces the root cause and the PDN fixes that made the ferrite beads unnecessary.