hot topics in esd

Simple star-tree networks, as shown here for USB2, should have wide applicability for cables carrying fast signals.

During the last four decades, damage to devices from electrical overstress (EOS) has confounded both IC suppliers and customers. The Industry Council on ESD Target Levels investigated numerous EOS root causes and established a white paper on the subject, JEP174 [1].

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).

2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.

This article explores the waveform specifications called out in the IEC 61000-4-2 standard.

Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products.

This is Part 2 of an article describing the difference between the electrostatic discharge (ESD) qualification requirements for automotive and standard commercial integrated circuits.

Integrated circuits intended for automotive applications have higher electrostatic discharge (ESD) qualification requirements than those intended for commercial and consumer electronics.

This article provides a high-level overview of the Industry Council paper “Survey on Latch‑up Testing Practices and Recommendations for Improvements,” which describes the full analysis of the collected responses and lays a path for potential adaptations needed to accommodate its use in future technologies and applications.